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#106595 - 07/24/16 10:04 PM Re: VME boards [Re: Edstrom]  
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Edstrom Offline
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I think I need some advice here. I have interrupts going from the serial controller to the gate array which directly interfaces the IPL0-IPL2 on the 68030. The gate array allows the interrupt level to be programmed individually for each connected device (8 local, 8 vme and some special interrupt sources) as well as edge/flank, assert level etc.

I have setup the serial device *int_cb to call the fga device which in turn figures out the level and calls its *int_cb which is connected to the fccpu30 board driver handler which looks like this:
Code:
WRITE_LINE_MEMBER(fccpu30_state::fga_irq_callback)
{
	LOGINT(("%s(%02x)\n", FUNCNAME, state));

	m_maincpu->set_input_line(INPUT_LINE_IRQ0, state & (1 << 0));
	m_maincpu->set_input_line(INPUT_LINE_IRQ1, state & (1 << 1));
	m_maincpu->set_input_line(INPUT_LINE_IRQ2, state & (1 << 2));
}

I get this far but: Firstly the state doesn't pass on the level, it is just asserted or not. So what is the best way pass the level?

Secondly, both the gate array and the serial device can provide the vector, how is the correct daisy_irq_ack() called?

#106722 - 08/01/16 09:32 AM Re: VME boards [Re: Edstrom]  
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Edstrom Offline
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I now got something that works, I have added an iack() callback function in the devices that will return the vector. These are configured from the board driver like this:
Code:
	/* FGA-002, Force Gate Array */
	MCFG_FGA002_ADD("fga002", 0)
	MCFG_FGA002_OUT_INT_CB(WRITELINE(fccpu30_state, fga_irq_callback))
	MCFG_FGA002_OUT_LIACK4_CB(DEVREAD8("duscc",  duscc_device, iack))
	MCFG_FGA002_OUT_LIACK5_CB(DEVREAD8("duscc2",  duscc_device, iack))

And there is also an INT callback from the device to the FGA chip like this:
Code:
	// DUSCC1&2 interrupt signal REQN is connected to LOCAL IRQ4&5 of the FGA-002 and level is programmable
	MCFG_DUSCC_OUT_INT_CB(DEVWRITELINE("fga002", fga002_device, lirq4_w)) 
	MCFG_DUSCC_OUT_INT_CB(DEVWRITELINE("fga002", fga002_device, lirq5_w))


I would also like to propose an iack() standard api where the vector is returned OR return codes for NO_VECTOR and IACK_TIMEOUT. I have implemented this for the hookup above and will add it to the rest of the devices unless someone tells me that it should be done differently, just let me know.

Last edited by Edstrom; 08/01/16 09:32 AM.
#106739 - 08/02/16 10:46 PM Re: VME boards [Re: Edstrom]  
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With two terminals and some early interrupt support from the DUSCC serial controller through the FGA002 asic to the Force CPU-30 I finally managed to get some response from the CPU-30 firmware (right terminal) beyond the bootstrap which was polled only (left terminal). I guess there are some board jumpers that directed the VxWorks roms to try to boot from disk and there should be a way to get a shell prompt directly from VxWorks I think, unless compiled without the shell...

#107166 - 09/07/16 09:48 AM Re: VME boards [Re: Edstrom]  
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Edstrom Offline
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Finally got the interrupts working on the Force CPU-30 through two rather new devices, the DUSCC and FGA ASIC, the biggest problem was due to I didn't understand the representation of interrupts in the 68k core and how the iack cycle worked in MAME. I am closer to understanding that now... I think. smile

So next step I will clean up the code, add all the interrupt sources and see where we are. I switched back from VxWorks to VMEPROM since it is the in house RTOS but that will be selectable by a port setting jumper. Also VxWorks imediatelly want to mount/boot a disk so I need to add the controller to get past that. It is possible that VxWorks requires some software on the hard disk also.

Last edited by Edstrom; 09/07/16 03:02 PM.
#107802 - 11/01/16 10:09 PM Re: VME boards [Re: Edstrom]  
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shattered Offline
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a bit of hacking and poking into its shared command ram with debugger, and fcscsi at least tries to read the floppy (but fails):

Code:
[:] void fcscsi1_state::led_w(address_space&, offs_t, uint8_t, uint8_t) [1f]
[:] uint8_t fcscsi1_state::tcr_r(address_space&, offs_t, uint8_t)
[:] void fcscsi1_state::tcr_w(address_space&, offs_t, uint8_t, uint8_t) [1d]
[:fdc] Event fired for timer TM_CMD
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_WAIT
[:fdc] SPINUP_DONE
[:fdc] SEEK_WAIT_STEP_TIME
[:fdc] SEEK_WAIT_STEP_TIME
[:fdc] Event fired for timer TM_GEN
[:fdc] SEEK_WAIT_STEP_TIME_DONE
[:fdc] SEEK_DONE
[:fdc] Event fired for timer TM_TRACK
[:mc68450] DMA#1: Operation Control write : 82
[:mc68450] DMA: Transfer begins: size=0x00000200
[:mc68450] DMA#1: Channel Control write : 80
[:fdc] Event fired for timer TM_SECTOR
[:fdc] Event fired for timer TM_CMD
[:fdc] read sector (c=88) t=0, s=1
[:fdc] SPINUP
[:fdc] SPINUP_DONE
[:fdc] SETTLE_DONE
[:fdc] SCAN_ID_FAILED

#107804 - 11/02/16 05:52 PM Re: VME boards [Re: Edstrom]  
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Edstrom Offline
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Nice! smile

#107811 - 11/04/16 12:41 AM Re: VME boards [Re: Edstrom]  
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shattered Offline
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First successful read smile

Code:
[:mc68450] DMA#1: Operation Control write : 82
[:mc68450] DMA: Transfer begins: size=0x00000200
[:mc68450] DMA#1: Channel Control write : 80
[:mc68450] DMA#1: End of transfer


Next up -- try to copy floppy to another floppy using this controller's BACKUP feature.

#107812 - 11/04/16 11:08 AM Re: VME boards [Re: Edstrom]  
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Edstrom Offline
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Still just playing around with the shared memory interface or are you adding code to the driver?! I guess I need to take on the VME bus again sooner or later so we can control that board from a CPU board smile

#107813 - 11/04/16 01:12 PM Re: VME boards [Re: Edstrom]  
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Adding code, yes ("1 file changed, 75 insertions(+), 6 deletions(-)") -- will submit that soon.

re: VME -- yes please smile Besta docs mention a few HD64384-based graphics boards, probably for CAD use, and I think the person who gave me iscsi docs may have manuals for those too.

#107818 - 11/05/16 12:09 AM Re: VME boards [Re: Edstrom]  
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Edstrom Offline
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Gah, I just started to look at the Force CPU-40 and it has the same FGA init but then the fun part starts with a table driven gibberish
setup of the DUSCC, dont't worry about the wrong baud rates, they make assumptions from CPU30 atm. There you go, a high level
language programmer has a table of constants and just changes the bits needed to get it to work. Compare that to the nice clean setup of the FGA in the beginning:

Code:
 * DUSCC #1 channel A setup 1 sequence FGA-002 firmware (polled i/o)
 *  A Reg 0f <- 00 - reset Tx Command
 *  A Reg 0f <- 40 - reset Rx Command
 *  A Reg 00 <- 07 - Async mode
 *  A Reg 01 <- 38 - Normal polled or interrupt mode, no DMA
 *  A Reg 04 <- 7f - Tx 8 bits, CTS and RTS, 1 STOP bit
 *  A Reg 06 <- 1b - Rx RTS, 8 bits, no DCD, no parity
 *  A Reg 05 <- 3d - Tx BRG 9600 (assuming a 14.7456 crystal)
 *  A Reg 07 <- 2d - Rx BRG 9600 (assuming a 14.7456 crystal)
 *  A Reg 0e <- 27 - TRxC = RxCLK 1x, RTxC is input, RTS, GPO2, crystal oscillator connected to X2
 *  A Reg 0b <- f1 - RTS low, OUT1 = OUT2 = high, RxRdy asserted on FIFO not empty
 *                   TxRdy asserted on FIFO not empty, Same Tx Residual Character Length as for REG_TPR
 *  A Reg 0f <- 00 - reset Tx Command
 *  A Reg 0f <- 40 - reset Rx Command
 *  A Reg 0f <- 02 - enable Tx Command
 *  A Reg 0f <- 42 - enable Rx Command
 *--- end of FGA setup sequence ---
 *  :dusccA Reg 00 <- ff CMR1 Async mode, no parity
 *  :dusccA Reg 01 <- 80 Local loopback mode
 *  :dusccA Reg 02 <- 20 Character Compare
 *  :dusccA Reg 03 <- 01 Not used in Async mode
 *  :dusccA Reg 08 <- 00 Counter/Timer Preset High 
 *  :dusccA Reg 09 <- 5f Counter/Timer Preset Low
 *  :dusccA Reg 0a <- 00 Counter Timer Control
 *  :dusccA Reg 0b <- 00 OMR 
Tx Residual Character Length is 1 bits
- TxRDY activated by FIFO not full
- RxRDY activated by FIFO not empty
- GP02, if configured as output, is: 1
- GP01, if configured as output, is: 1
- RTS, either pin if configured as output, is: 1
 *  :dusccA Reg 04 <- 00 TPR Transmit Parameter Register
- RTS 0
- CTS 0
- Stop Bits 1
- Data Tx bits 5
- RX:32x
- TX:32x
 *  :dusccA Reg 05 <- f0 
- External source: TRxC
- Transmit Clock: 32x own channel C/T - not implemented
- BRG Tx rate 50 assuming a 14.7456MHz CLK crystal
 *  :dusccA Reg 06 <- 00 
- RTS output 0      
- Strip Parity 0    
- DCD/SYNIN input 0 
- Data Rx bits 5    
- RX:32x  
- TX:1x   
 *  :dusccA Reg 07 <- 0a 
- External source: RTxC
- Receiver Clock: 1x External - not implemented
- BRG Rx rate 2000 assuming a 14.7456MHz CLK crystal
- RX:1x
- TX:1x
 *  :dusccA Reg 04 <- 00 
- RTS 0
- CTS 0
- Stop Bits 1
- Data Tx bits 5
- RX:32x
- TX:32x
 *  :dusccA Reg 05 <- f0 
- External source: TRxC
- Transmit Clock: 32x own channel C/T - not implemented
- BRG Tx rate 50 assuming a 14.7456MHz CLK crystal
 *  :dusccA Reg 06 <- 00 
- RTS output 0      
- Strip Parity 0    
- DCD/SYNIN input 0 
- Data Rx bits 5    
- RX:32x  
- TX:1x   
 *  :dusccA Reg 07 <- 8a 
- External source: TRxC
- Receiver Clock: 1x External - not implemented
- BRG Rx rate 2000 assuming a 14.7456MHz CLK crystal
- RX:1x
- TX:1x

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