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#110942 - 10/01/17 08:39 PM Re: BBC Tube WIP [Re: crazyc]  
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Pernod Online content
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Originally Posted by crazyc
Maybe if it was AT compatible enough to run Windows in standard mode it would make more sense.

I have a few floppy images of Windows 1.02, 1.03, 2.03, 2.1 for the RM Nimbus, will see what it does with them.

Edit: Windows complains with 'This version of Windows needs MS-DOS 3.1 or later'

Last edited by Pernod; 10/01/17 09:33 PM.

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#110943 - 10/02/17 02:06 AM Re: BBC Tube WIP [Re: Pernod]  
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Dunno about the BBC Tube video but the Nimbus graphics adapter is rather odd and I'm sure that even if Windows did start it wouldn't be able to draw anything. Without an PIC, PIT or CGA much XT software is out too (of course that's the problem that all non-PC compatible MSDOS computer makers ran into and why they all gave up).

Last edited by crazyc; 10/02/17 02:06 AM.
#111029 - 10/11/17 11:43 AM Re: BBC Tube WIP [Re: Pernod]  
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This may be out of my comfort zone, but if I were to implement the NS32016 cpu can anyone give me some guidance? Is there an existing cpu that I can use as a base starting point?

http://bg-electronics.de/datenblaetter/Schaltkreise/NS32016.pdf


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#111030 - 10/11/17 12:12 PM Re: BBC Tube WIP [Re: Pernod]  
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I don't know that I'd directly base it on any existing CPU core. Your best bet is to look at how a CPU familiar to you is implemented and try to follow (and copy) the structure. That's a little hard because some newer CPU cores (e.g. the 6502 family) are made using a python program to generate the actual opcode handlers. That's generally smart, but it also obfuscates things a bit.

#111031 - 10/11/17 12:47 PM Re: BBC Tube WIP [Re: Pernod]  
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The 6805 family are a "traditional" MAME CPU with an execute loop and opcode handler macros in a table with no regards for interruptible instructions. The mcs40 (4004/4040) is probably the simplest case of a CPU core implemented at bus cycle level. Each phase of the instruction cycle is emulated, and all bus signals are exposed (this is actually necessary for the INTELLEC 4 and Flicker drivers). As ArBee says, the 6502 and H8 are obfuscated because of the additional layer of indirection. However this allows them to get interruptible instruction handling relatively easily for a more CISC architecture.

#111052 - 10/15/17 12:09 AM Re: BBC Tube WIP [Re: Pernod]  
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Originally Posted by Pernod
The 80286 2nd processor was never commercially released, and is only found in a few examples of the ABC 310 that exist. What we know is that it used the same boot ROMs that were found in the later Master 512, and had 1MB RAM. All photos out there seem to be of the same board and no schematics have been found so a little reverse engineering of the boot code was required. The boot ROM detects whether it is running on 80186 or 80286 and acts differently accordingly.

There is no known software specifically developed for the ABC 310 so am running the Master 512 System disk which shows it running on the 80286 and behaves differently from the Master in my previous post.


I've seen some suggestions that the ABC 310 was intended to run Concurrent DOS, which might have been able to use protected mode.

While DOS Plus contains two sets of Tube client code (for the 186 and 286), the 286 code is buggy for type 2 / 3 memory transfers initiated by the host. The transfer address is in the data segment, but the transfer code accesses the corresponding address in the code segment.

#111078 - 10/16/17 11:14 AM Re: BBC Tube WIP [Re: John Elliott]  
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Originally Posted by John Elliott
I've seen some suggestions that the ABC 310 was intended to run Concurrent DOS, which might have been able to use protected mode.

Yeah, I'm not sure it was ever completed though as I've found no evidence that it ever existed. The machine was shown at the PCW show in '84 and looked like it was running some Desktop Manager, maybe GEM. Then there's a review of a preview model in '85 that was running Concurrent CP/M 3.1 as Concurrent DOS was not yet ready.


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#111273 - 11/14/17 10:52 AM Re: BBC Tube WIP [Re: Pernod]  
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Another co-processor for the collection, the ARM Evaluation System connected to a Model B and Master respectively.
[Linked Image] [Linked Image]

Last edited by Pernod; 11/14/17 10:52 AM.

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#111507 - 12/05/17 02:19 PM Re: BBC Tube WIP [Re: Pernod]  
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Originally Posted by Pernod

When this board starts the 68008 is HALTed until 6502 has setup vectors and code in the shared RAM to allow the 68008 to start. The 68008 is then told to RESET by writing 0x34 into the 6821 Control Register B which should trigger my CB2 handler to perform the RESET. The CB2 handler is not triggered though due to CB2 being 0 when started and writing to the Control Register also setting it to 0, CB2 handler is only called when it changes state.

From someone else's notes I have 'Pull up resistor R12 makes CB2 high when it's configured as an input', which can be seen on the RESET/HALT lines from the 68008 on page 2 of the above circuit diagram. The RESET 68000 is connected to CB2 of the 6821 on page 3. How can I implement this?


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#111508 - 12/05/17 03:48 PM Re: BBC Tube WIP [Re: Pernod]  
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AJR Offline
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I think you'll just have to push it manually at machine start, by writing something like m_pia->cb2_w(1). Remember that one of the M68000's quirks is that its RESET line is both an input and an open-collector output, so if the 68008 code can use RESET instructions and CB2 gets reconfigured as an input, you may also have to add a handler for that.

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