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#108028 - 11/27/16 10:41 PM Re: SVN builds - new driver flood [Re: Anna Wu]
Edstrom Offline
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Registered: 08/11/15
Posts: 298
I am looking at the GMX Micro20 68230 problem right now and it seems the timer test first awaits a pulse on any PitPB input and when that one is found it sets up the timer and make a btst #2, PitPC. The driver doesn't map any input on these ports so RB do you by any chance have schematics for what can be connected there?
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#108029 - 11/27/16 11:07 PM Re: SVN builds - new driver flood [Re: Anna Wu]
R. Belmont Offline

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Registered: 03/17/01
Posts: 15487
Loc: USA
I don't have schematics, just PCB photos and a technical manual with the address map etc. I'll see if they say what's connected to the PIT inputs.

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#108031 - 11/28/16 12:48 AM Re: SVN builds - new driver flood [Re: R. Belmont]
Al Kossow Offline
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Registered: 01/06/11
Posts: 147
Originally Posted By R. Belmont
I don't have schematics, just PCB photos and a technical manual with the address map etc. I'll see if they say what's connected to the PIT inputs.


the schematic is in the back of the technical manual

tin comes from a Seiko programmable clock chip


Edited by Al Kossow (11/28/16 12:50 AM)

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#108033 - 11/28/16 01:45 AM Re: SVN builds - new driver flood [Re: Anna Wu]
R. Belmont Offline

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Registered: 03/17/01
Posts: 15487
Loc: USA
Ahh, yeah, ports B and C on the 68230 connect to an MSM58321 clock chip, which also provides the TIN timing source. So this isn't a 68230 defect at all smile (Or at least right now it's not).

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#108034 - 11/28/16 02:03 AM Re: SVN builds - new driver flood [Re: R. Belmont]
Al Kossow Offline
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Registered: 01/06/11
Posts: 147
Originally Posted By R. Belmont
Ahh, yeah, ports B and C on the 68230 connect to an MSM58321 clock chip, which also provides the TIN timing source. So this isn't a 68230 defect at all smile (Or at least right now it's not).


the timing source isn't obvious from the schematic. it's from a Seiko SPG8651 (U1), which is why the data sheet is in the directory. They have it jumpered for 100Hz

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#108035 - 11/28/16 02:22 AM Re: SVN builds - new driver flood [Re: Anna Wu]
R. Belmont Offline

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Registered: 03/17/01
Posts: 15487
Loc: USA
Oh, interesting. Now I see how that works.

Edstrom: regarding the PIT, it would be helpful if the port lines were brought out individually. So you have MCFG_PIT68230_PA0_CB() and then a series of public WRITE_LINE members like rxa_w and friends in z80scc.

Since there is no way I can see to send TIN to the PIT and the PIT doesn't ever output H4, that means I *am* actually stuck on it. I've committed a revised micro20.cpp that makes the lack of those things obvious and testable, good luck smile


Edited by R. Belmont (11/28/16 03:15 AM)

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#108036 - 11/28/16 10:21 AM Re: SVN builds - new driver flood [Re: Anna Wu]
Edstrom Offline
Senior Member

Registered: 08/11/15
Posts: 298
I'll have a stab at it. Note that the 68230 driver doesn't do interrupts or full timers yet so it may take some time (pun intended) to implement. I will write something up for the individual input pins too to avoid using trampoline latches in the board drivers. Thx for a good test case! smile


Edited by Edstrom (11/28/16 10:22 AM)
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#108037 - 11/28/16 02:17 PM Re: SVN builds - new driver flood [Re: Anna Wu]
Edstrom Offline
Senior Member

Registered: 08/11/15
Posts: 298
Adding handlers for port B and C that just returns a simple running call counter that eventually toggles the bits the code is
looking for I get a slightly different response:



H4 is never enabled in PGCR and in fact the code just jumps in and uses the PIT as is. I did implement and H4/H2
code but it never executed as they were disabled. But I have also added reset callout for H4 and when chaninging
PBCR so you may get some calls to your callbacks now.

Will take a look at TIN now, I saw that the test starts polls bit #2 at Port C in port mode, just to see if there is a clock
at all I would assume.


Edited by Edstrom (11/28/16 02:19 PM)
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#108038 - 11/28/16 03:25 PM Re: SVN builds - new driver flood [Re: Anna Wu]
R. Belmont Offline

Very Senior Member

Registered: 03/17/01
Posts: 15487
Loc: USA
Yeah, it's possible H4 isn't (yet) touched by the software, but it's supposed to be high on reset. H4 controls if the 100 Hz timer causes an IRQ 6 on the 68020 (it always clocks TIN on the PIT, and if H4 is low then the IRQ 6s occur).


Edited by R. Belmont (11/28/16 03:27 PM)

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#108055 - 11/29/16 10:36 PM Re: SVN builds - new driver flood [Re: Anna Wu]
Edstrom Offline
Senior Member

Registered: 08/11/15
Posts: 298
Ok, PR is now available with PIT improvements, needs a pulse on port B from somewhere, new functions

void update_tin() and
void p[a/b/c]_update_bit(uint8_t bit, uint8_t state);

should cover the need for hooking up the micro20, I have not tested it since I didn't know how to hook up the IRQ 6
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