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#66261 - 12/16/10 03:33 PM SNES DSP-1/A/B/2/3/4: need help emulating uPD77C25  
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byuu Offline
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Okay, as some of you know, Dr. Decapitator was successful in dumping the DSP-1B program ROM from Ballz 3D, and we already have the data ROM.

The chip is a NEC uPD77C25. An emulator for this chip will allow instant low-level, bit-perfect, timing-perfect emulation for the following games:

SNES DSP-1/1A/1B:
* Ace Wo Nerae
* Armored Trooper Votoms
* Ballz 3D (1b)
* Battle Racers
* Bike Daisuki! Hashiriya Kon
* Final Stretch
* Korean League
* Lock On/Super Air Diver
* Michael Andretti's Indy Car Challenge
* Pilotwings (1... possibly also 1b)
* Super 3D Baseball
* Super Air Diver 2
* Super Bases Loaded 2
* Super F1 Circus Gaiden
* Super Mario Kart(1/1b depending on version)
* Suzuka 8 Hours
* Syutoko Battle Racing 2
* Syutoko Battle Racing 94

SNES DSP-2:
* Dungeon Master

SNES DSP-3:
* SD Gundam GX (HLE is currently unplayable)

SNES DSP-4:
* Top Gear 3000

SEGA arcade:
* Air Rescue (uPD77P25, PROM variant)

Unknown:
* Prose 2020 Speech Synth (uPD77C20, backward-compatible)

It will also allow us to kill off a good 213KB of HLE, GPL2/non-commercial code bloat in our emulators, replaced with a simple 20KB processor core.

I have written a full emulator and disassembler, but the emulator is far from perfect because the documentation sucks and is too confusing to me. It's still too poor to actually play anything.

I really need some help from one of the MAME/MESS veterans here if at all possible. I have my emulator source, the disassembly, and all technical sheets up on my forum, under the development section. If you don't have access and want to work on this, register there and PM me, and I'll add you.

If we can get this working, I'll give you guys the uPD77C25 core under the public domain so that you can emulate SEGA Air Rescue, and also use it in MESS:SNES.

Thanks in advance laugh

#66262 - 12/16/10 08:02 PM Re: SNES DSP-1/A/B/2/3/4: need help emulating uPD77C25 [Re: byuu]  
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Richard Bannister Offline
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Nice.


Noli umquam docere porcum cantare; perdes tempus et irritabis porcum.
#66263 - 12/16/10 08:06 PM Re: SNES DSP-1/A/B/2/3/4: need help emulating uPD77C25 [Re: Richard Bannister]  
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R. Belmont Online content
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We have full dumps for DSP-2/3/4? Or is that counting unhatched chickens? smile

#66264 - 12/16/10 08:37 PM Re: SNES DSP-1/A/B/2/3/4: need help emulating uPD77C25 [Re: R. Belmont]  
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balrog Offline
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I'm told that DSP-2/3/4 are coming smile

#66265 - 12/16/10 09:09 PM Re: SNES DSP-1/A/B/2/3/4: need help emulating uPD77C25 [Re: balrog]  
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byuu Offline
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Originally Posted By Balrog
I'm told that DSP-2/3/4 are coming smile


As soon as we can raise $750 in donations wink
I'm going to pitch in $150 myself this time, and Lord Nightmare is going to donate the cartridges, so we need $600 more. If you're interested in helping:
http://board.byuu.org/viewtopic.php?f=16&t=1249

My emulation is now good enough to get in-game on Super Mario Kart, but I'm completely stumped at this point. Still, if we can get past these hurdles, we can literally plug in and play the DSP-2,3,4 games.

Official docs:

http://www2.renesas.eu/_pdf/U12675EJ7V0DS00.PDF
http://docs.google.com/viewer?url=http%3A%2F%2Fwww.datasheetarchive.com%2Fpdf%2Fgetfile.php%3Fdir%3DDatasheets-8%26file%3DDSA-152781.pdf%26scan%3D

Current questions:

Multiplication happens after each opcode, K*L is put into M,N. But it mentions the result is 30-bit with a sign bit. Isn't that the same thing as 31-bit? Or is it possible it is acting like the sign bit of the flag registers, and just mirroring the highest bit?

What is the order of operations for OP/RT? Take this example:

Code:
4eb inc a
mov a,rp

To dump the data ROM correctly, we have to do the mov first, and the inc second.
The way I've implemented it was to do the inc read, then the mov read, then the inc write, then the mov write.
Both have the ability to manipulate both the IDB register and any shared registers.
It is at least somewhat clear from the documentation that the DPL, DPHM and RP adjustments happen at the end of the opcode.

How in the hell do we calculate the OV1 flags? The documentation says it's set to 1 if there were an odd number of the three overflows. What three overflows?

What about the S1 flag? Is it set to 1 on a positive overflow, or set to 1 on a negative overflow? What happens if there is no overflow, does it get set to zero always then?
The SGN register may be a useful hint to figuring this one out.

Am I even calculating OV0 correctly?

CMP (one's complement) is just !Q, right? They would say NOT if they wanted ~Q.

How exactly does XCHG work? The document says it's an 8-bit exchange. Which 8-bits, the top eight or the bottom eight? It updates the S0 flag which is suspicious for the bottom eight.

What is up with KLM mode? The nicer doc says you read from RAM[DP | 0x40], while the uglier one says that you read from RAM[(DP & 0x3f) | 0x40]. They list it as HiRAM, yet it forces D6=1 rather than D7=1. And just out of curiosity, why the fuck does it force D6=1? What possible use is that?

The stack has four levels, and it is LIFO. So what happens when you pull an address off the stack? Does the now empty slot at the end get set to zero, or keep the previous address, or does it act more like a ring buffer and move the old first value to the last value?

When SR.DRC=0 (eg 16-bit DR transfer mode), does RQM get cleared for each 8-bit write, or only after two 8-bit writes (eg after a full 16-bit transfer)?

What happens to the high 8-bits of the 16-bit DR register when you write to it from the S-CPU in 8-bit DR transfer mode? Does it keep whatever was there, or is it forced to zero ala 65816 index registers?

#66266 - 12/16/10 11:19 PM Re: SNES DSP-1/A/B/2/3/4: need help emulating uPD77C25 [Re: byuu]  
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Lord Nightmare Offline
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Originally Posted By byuu

What is up with KLM mode? The nicer doc says you read from RAM[DP | 0x40], while the uglier one says that you read from RAM[(DP & 0x3f) | 0x40]. They list it as HiRAM, yet it forces D6=1 rather than D7=1. And just out of curiosity, why the fuck does it force D6=1? What possible use is that?


This is a holdover from the UPD7720, the predecessor to the 7725 which had half as much ram; on the 7720 it was the HIGHEST bit of ram which was held high for KLM transfers; on the 7725, to retain compatibility with 7720 code, the bit held high is ram a6, while ram a7 can be set to whatever the user wants.

LN


"When life gives you zombies... *CHA-CHIK!* ...you make zombie-ade!"
#66269 - 12/17/10 06:02 AM Re: SNES DSP-1/A/B/2/3/4: need help emulating uPD77C25 [Re: byuu]  
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Lord Nightmare Offline
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Originally Posted By byuu

What happens to the high 8-bits of the 16-bit DR register when you write to it from the S-CPU in 8-bit DR transfer mode? Does it keep whatever was there, or is it forced to zero ala 65816 index registers?


This is gone over in some detail on the Elsevier paper about the uPD7720; when in 16 bit mode, writing to DR will send the MSB byte first, then the LSB byte; in 8 bit mode, writing to DR will send the LSB byte only; this makes interfacing an 8-bit dac with the chip without added circuitry a bit of a chore, since you have to shift the data first before writing to DR.

When in 8 bit mode, ***I AM GUESSING*** writes from snes or other host cpu TO the data register behave exactly the same, only populating the low 8 bits of DR and high 8 bits are zeroed. When in 16 bit mode, sending data is probably MSB first but the existing dsp1 simulation code should tell for sure.

LN


"When life gives you zombies... *CHA-CHIK!* ...you make zombie-ade!"
#66271 - 12/17/10 02:21 PM Re: SNES DSP-1/A/B/2/3/4: need help emulating uPD77C25 [Re: Lord Nightmare]  
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ReadOnly Offline
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I might donate $75. PM me.

#66274 - 12/17/10 08:13 PM Re: SNES DSP-1/A/B/2/3/4: need help emulating uPD77C25 [Re: ReadOnly]  
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judge Offline
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Apparently a combination of the OVA0, SA1, and OVA1 flags can be used to determine if one or more of the past 3 arithmetic instructions had an overflow.

The docs don't clearly describe how that calculation is done though.

That'll be a nice challenge wink

In KLM mode, bit 6 being forced high is mostly done to keep it 7720 compatible; which had 128 bytes of the RAM and the 7725 256 bytes.

I think XCHG exchanges the top and bottom 8 bits.

Last edited by judge; 12/17/10 08:28 PM.
#66275 - 12/18/10 12:53 PM Re: SNES DSP-1/A/B/2/3/4: need help emulating uPD77C25 [Re: judge]  
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byuu Offline
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Cydrak just popped up out of the blue with almost a dozen bugfixes to my processor core.

Super Mario Kart is now fully playable with low-level DSP-1B emulation.

http://i73.photobucket.com/albums/i221/byuusan/supermariokart.png
(ignore the framerate, that was on my underclocked Atom netbook.)

As soon as we can raise the $750 to get the other three, they should be immediately playable and perfected. Again this is most important for the DSP-3, currently unplayable through our HLE simulation.

Once done, only two SNES games will remain unplayable (or for that matter, have any known bugs at all), and both of them will start with "Quick-move Shogi Match with Nidan Rank-holder Morita."

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