I'm overhauling the heck out of pds30_30hr.cpp, one of the oldest-style remaining NuBus video cards now that the original source and documentation is circulating (
https://github.com/ZigZagJoe/Color30HR-ROM). Even with the encryption on the registers resolved (Kale thinks SVGA is bad, LOL), I can't get the numbers to work.
Some decrypted register values, validated against the numbers in the source (which are all hard-coded).
Stock Mac-style 640x480 (30.240 MHz pixel clock). Htotal should be in the vicinity of 896, and Hvis is of course 640.
H front porch interval: 63
Half of H sync: 31
H back porch minus NS: 66
H line ("[# of pixels per line - (FS1+FS2)] divided by 2 : 205
HSync22 ("FS1+FS2+NS+H Front Porch+H Back Porch+Line/2"): 370
Row MSBs ("Row transfer address MSBs"): 234
FS1 ("Format run pipe fill"): 1
FS2 ("Format run off"): 11
NS ("Period in H back porch interval to begin holding off DAC access to prevent snow"): 17
If you assume all values are 1 less than the real number (which is plausible), I can torture these values to almost work:
H line (206 * 2) = 412 + (FS1 2 + FS2 12) = 426 *2 (arbitrary) = 852 Htotal (too far off, but play along) - (HFP 64 + HSync (x2) 64 + (HBP+NS) 84) = 640 visible.
But this blows up for the 640x480 SVGA mode (25.175 MHz pixel clock):
HFP: 15
HSync: 47
HBP: 16
HLine: 238
HSync22: 304
Row MSBs: 237
FS1: 1
FS2: 11
NS: 16
800x600 @ 72 Hz SVGA (57.283 MHz pixel clock):
HFP: 31
HSync: 36
HBP: 70
HLine: 92
HSync22: 0
Row MSBs: 490
FS1: 7
FS2: 9
NS: 16
Mac 832x624:
HFP: 12
HSync: 18
HBP: 79
HLine: 128
HSync22: 0
Row MSBs: 498
FS1: 2
FS2: 4
NS: 18
1024x768 (65 MHz pixel clock):
HFP: 29
HSync: 32
HBP: 54
HLine: 163
HSync22: 0
Row MSBs: 499
FS1: 6
FS2: 8
NS: 12
If anyone can get these numbers to work please let me know how :-)
