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#22723 06/30/06 07:07 PM
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Why did you change Seicross to mapper 181? It works fine here under mapper 185.

This is what I do:
mapper writes:
- if the cart contains more than 1 chr bank, bankswitch like CNROM.
- toggle the chr enabled bit (it's enabled at power up)

reads from chr rom (PPU $0-$1fff):
- if chr is disabled, and the PPU is not rendering, put the high 8 bits of the PPU address OR $80 (open bus, $80 for PPU addressbus is 15 bits wide) into the PPU read buffer.

Let me know if you'll change it back to 185, so I won't follow suit by adding mapper 181 as a duplicate of 185.

#22724 07/01/06 02:05 AM
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I changed it to 181 to keep up to sync with FCEUmm but I better change it back now that I learned a more accurate way of handling the CHR enable/disable switch.

#22725 07/01/06 02:57 AM
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It's all guesswork/trial and error, I can't know if my method is accurate, though it makes more sense to me than CaH4e3's way.

#22726 07/01/06 03:26 AM
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Yeah, more sense than this eyesore I'd say: smile

// Bird Week : $C020:F0 $C021:0F
// B-Wings : $B69F:00 $B69E:33
// Bomb Jack : $8071:00 $8072:11
// Seicross : $80DF:21 $80DE:20
// Sansuu 2.. : $805C:20 $805D:22
// Sanssu 2.. : $803F:20 $8040:22
// Sanssu 3.. : $805C:00 $805D:FF
// Spy vs Spy : $8090:13 $8091:21

openBus = !(data & 0x03) || (data == 0x13);

Which worked fine until Seicross came along and ruined the logic.

#22727 07/02/06 01:24 AM
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Quote:
- if chr is disabled, and the PPU is not rendering, put the high 8 bits of the PPU address OR $80 (open bus, $80 for PPU addressbus is 15 bits wide) into the PPU read buffer.
That doesn't make sense. The address bus, first of all, is only 14 bits wide (every pinout I've seen only shows A0-A13). The VRAM address register ($2006) is 15 bits wide, but $2007 accesses ignore the most significant bit and use the lower 14 bits to set the address bus.

Typically, open bus results in the data lines D0-D7 retaining their previously set value. For the CPU this is usually (but not always) the upper eight bits of the effective address because that's what the CPU last fetched from memory prior to the open bus. However, the PPU doesn't work that way - its data lines never contain any part of the effective address. Thus, an open bus situation on the PPU would return something completely different.


"Last version was better," says Floyd. "More bugs. Bugs make game fun."
#22728 07/02/06 05:46 AM
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Indeed, it's 14 bits wide, my mistake. (the method also works fine with OR $C0).

This open-bus situation is not for the usual CPU->PPU connection, as with the lower 5 bits of the PPU status register, but instead it's PPU->chrrom, so I was hoping/guessing it to be different.

#22729 07/10/06 06:11 PM
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I see you're putting $FF into the read buffer if CHR is disabled, that does seem even more believable. Me and my complicated guesses :p


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