Self-test on this machine is very, very paranoid -- I think I've found a emulation bug in i8255.cpp
And there are two more bugs, apparently. Datasheet shows that INTR bit should go high only after STB is deasserted (goes high); and that asserting STB should always load data into input latch. With these changes, keyboard interface test is happy.
Floppy interface reverse engineering notes, for future reference. (LLE is not working yet.)
Since 765 is not designed to work with 8 inch drives, the MCU likely intercepts SEEK and STEP signals and converts them to motor phase signals.
8150 r/w ?? reset mcu? needs delay
8152 w ?? reset 765? needs delay
8154 w wrap
8156 r wrap
8158 r 765 MSR
815A r/w 765 FIFO
815C r/w mcu CSR -- mcuppi PA
0.R3 ?? head movement requested (b0, b1)
0.R6 ?? timer ticks?
0.R7 ?? timer ticks?
1.R0 ?? initial value 0x20
1.R1 reply queue pointer, initial value 0x20
1.R2 ?? timer ticks? initial value 0x80 (bit 7 -- ??)
1.R3 ?? current phase
1.R4 ?? current phase
mcu memory locations:
20-27 cpu reply queue
28 ?? temp area for cmd 4
31-33 ?? save area used by INT handler
37-39 ?? save area
3c ?? drive ready status? current rpm?
3d ?? initial value 0xd9
3e ?? timer related, initial value 0x5c
3f ?? initial value 0x65
int handle incoming command?
t0 ?? irq source
t1 ?? SEEK from 765
P1 0-2 + to ppi - address bits + chip select
3 + from drive 0 - index
4 + from drive 1 - index
5 to drive 0 - gate for ??
6 to drive 1 - gate for ??
P2 0 + head engage signal - to drive 0
1 + head engage signal - to drive 1
3-4 access 0/1 drive 0 ??
5-6 access 0/1 drive 1 ??
PB0 ?? to drive 0
PB1 ?? to drive 1
PB3 ?? to drive 0
PB4 ?? to drive 1
PB5 ?? IRQ to CPU? ?? to gate for 765 signals
PC0 i/o in from 765 ?? STEP ??
PC1 i/o in from 765 ?? DIR ??
PC2 i/o in
PC3 INTR to ?? IBF, OBF gated by INTE2, INTE1
PC4 ~STB from ??? set to load data into PA
PC5 IBF to ??? data loaded into PA
PC6 ~ACK from ??? set before reading data in PA
PC7 ~OBF to ??? data available in PA