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#112870 03/14/18 04:59 PM
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https://github.com/cuavas/mame/tree/dsp16

The DSP16A is an interesting chip. It's like the great granddaddy of VLIW and EPIC.
  • The instruction set is explicitly parallel, and it can manage a 16*16->32 multiply, a 32+36->36 addition, a 12+12->12 addition, a 16+16->16 (9+9->9 on DSP16) addition, two 8-bit increments, a ROM fetch, and a RAM access in a single cycle. Yes, the word is and, although there are limitations on the exact combinations you can use.
  • There are effectively no general-purpose registers - every register has an assigned role, although in some cases a few registers are interchangeable (e.g. the two accumulators and four RAM pointers).
  • It has dedicated silicon for saturation and rounding.
  • It has an on-board pseudorandom sequence generator.
  • It normally overlaps the ROM fetch for the next instruction with the current instruction, but it has a manually managed 15-instruction cache in the control unit. When executing from cache, it can overlap a ROM data fetch for the next instruction with the current instruction for higher throughput. By executing a tight loop from cache, you can make a very fast FIR filter with coefficients in ROM.
  • Although the DSP16 can only use internal program ROM or external program memory, but not both at the same time, the DSP16A can access external program memory while the internal ROM is enabled (QSound uses this to read sample data).
  • It supports multi-master time-division multiplexed synchronous serial protocols, making it ideal for processing circuit-switched voice calls.
  • The QSound DSP runs at 30MHz (60MHz clock input divided by two). On CPS2, it's already clocked at almost three times the speed of the main 68k CPU, it can issue an instruction every one or two cycles, and it can do up to four operations per instruction. The QSound DSP is far more powerful than the main CPU.


I've implemented almost all of the instructions, and enough of the onboard peripherals to for the QSound program to work. It's machine cycle-granular and fully interruptible. I think I've got a logic bug making looping samples screw up or something, so it doesn't sound right. It also has very high CPU requirements now that it's trying to run a 4-way explicit DSP at 30MHz.

Also, I want to meet the guy who wrote the program and buy him a beer. There are some pretty amusing techniques in the code.

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Great !

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Originally Posted by Vas Crabb

Also, I want to meet the guy who wrote the program and buy him a beer. There are some pretty amusing techniques in the code.


https://en.wikipedia.org/wiki/Brian_L._Schmidt


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Exciting stuff! Let me know if you need any digital audio captures from the hardware for verification purposes. I'm sure I can arrange something smile

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Thanks for the offer Phil - it might be useful. I've force-pushed an update, and it's working much better now (issue with interrupt emulation, and AM_MIRROR covering too many bits). It just seems to be reading samples from the wrong place in ROM or something.

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And with a bit more tweaking, it reads samples from the right place! Effects sound right to me. I guess it's time to think about making it fast now...

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http://arcade.vastheman.com/qsound.wav
The QSound jingle at 8s plays 16 channels simultaneously with effects, then you can hear the first few seconds of the attract music with spatialiser in effect from about 18s (it's a 30-second capture of sfz2alj with QSoundâ„¢ DSP emulated).

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Oh, while I think of it Phil, do you have the gear to check what the glue logic presents on the low eight data lines during sample reads? The DSP wants 16-bit signed samples, and the ROM contains 8-bit signed samples that need to end up in the most significant byte. I want to know what ends up in the least significant byte (I'm emulating it as byte smearing).

The lines in question are RB00 to RB07, on pins 35, 36, 37, 38, 39, 40, 42 and 43 (information manual p7-7 or 162 in PDF numbering). I want to know if they're always tied high/low, or if they're somehow affected by what's on lines RB08 to RB15, on pins 44, 45, 46, 47, 48, 49, 50 and 51. The DSP samples RB00 to RB15 on falling edges of the CKO output (pin 33, see p7-10/165). There are no read/write strobes as it's designed to be used with dumb ROM.

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I put together a quick demo video of the new audio improvements: https://www.twitch.tv/videos/238950989
It goes SFA2 old, SFA2 with QSound, SFA1 old, then SFA1 with QSound. Seems like SFA2 is a lot more noticeable than SFA1, but I'd put that down to them having more time to work with QSound in general.

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And with a bit more love, the new DSP16 core and disassembler are in mainline, although it still isn't enabled for QSound due to the current performance.

Phil, I thought of another thing I'd like traced on a real game (doesn't matter whether it's CPS1.5/CPS2/ZN1/ZN2). Could you capture the following for a couple of sample periods and show a graph:
  • OSE (DSP pin 52, output)
  • OCK (DSP pin 59, output)
  • OLD (DSP pin 60, output)
  • SYNC (DSP pin 62, input?)
  • PSEL (DSP pin 72, output)
  • WS (TDA1543 DAC pin 2, input)

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