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shattered #117686 08/18/20 12:28 PM
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Cool, do you know what the VME boards are that is being probed, eg hcww, cww and md10?


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Edstrom #117689 08/18/20 05:19 PM
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cww is Force ISIO (8 smart serial ports).

hcww is 8 dumb serial ports + centronics port + Intersil ICM7170 clock.

md10 is possibly a SSD or just a RAM disk.

Edstrom #117698 08/21/20 06:34 PM
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Besta is known to have used Force AGC-1 graphics board, and had X server for it Adding that shouldn't be too hard -- https://www.mirrorservice.org/sites...ters/800106_AGC-1_Users_Manual_Aug86.pdf

Edstrom #119929 10/28/21 08:03 AM
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I'm working on a driver for the Motorola SYS1121, a combination of an MVME120, MVME050 SYSCON, and a disk controller. I can get the MVME120, as a slot device, booting to the 120bug console with a little poking in the debugger (it doesn't fully pass one of the exception tests during a cold boot, but I can bypass it.)

[Linked Image from i.imgur.com]

I'd like to try to hook up the bus logic and get it talking to another card in the VME address space but I'm not sure how well the VMEbus emulation in MAME works, or if it works at all. It doesn't look like it's hooked up in any of the other VME slot devices.

The firmware and manuals are all on Bitsavers and m88k. Unlike the later MVME SBCs, the 120’s bus logic is all in PALs and TTL.

Last edited by Luigi30; 10/28/21 09:47 AM.
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Luigi30 #120046 11/17/21 08:24 PM
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There is a lot lacking in regards of VME specials support but if you look at mame/drivers/miniforce.cpp you get a grasp how a multiboard system is set up as a driver. The boards are implemented as slot devices under bus/vme and can as such be populated in the miniforce.cpp driver or any other VME bus driver. With other words, if you make it a slot device instead of driver you can use miniforce.cpp driver as the VME chassi. But the SYS1121 probably had its own chassi which could be the driver you want to write. Checkout devices/bus/vme/vme_fccpu20.cpp for an example of a VME CPU slot device


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Edstrom #120047 11/17/21 08:58 PM
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MAME's core started out where it couldn't do a bare slot bus where one or more of the cards are bus masters. I don't *think* that's true anymore and you could now create a driver where all it does is host VME slots (or S-100 or whatever), but I haven't tried it either. I do suspect in the degenerate case where you run a bare slot bus with no cards and no CPUs the scheduler would still get angry.

I'd recommend making a SYS1121 driver as Edstrom said that has a VME bus and two of the slots are fixed to start with the MVME120 and MVME050 cards fixed in the slot. (I'm assuming multiple disk controller cards are possible; if there's a specific one, put that in a third slot). The driver itself would be tiny and you'd be following how the real hardware works.

Luigi30 #120052 11/18/21 09:40 AM
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Quote
I'd like to try to hook up the bus logic and get it talking to another card in the VME address space but I'm not sure how well the VMEbus emulation in MAME works, or if it works at all. It doesn't look like it's hooked up in any of the other VME slot devices.
The VMEbus emulation is a plain address map that currently only support different bus widths, not daisy chaining or dynamic bus cycles or the other VME signals. If you look at the devices/bus/vme/vme_mzr8300.cpp you can see how to hook up 8 bit read/write handlers from an I/O board into the memory map of the CPU board devices/bus/vme/vme_mzr8105.cpp. The intention is that you need a CPU board that can access the VME bus spaces as required for the I/O board or the I/O board would not be able to add itself in a chassi.
Quote
The firmware and manuals are all on Bitsavers and m88k. Unlike the later MVME SBCs, the 120’s bus logic is all in PALs and TTL.
This is a lot of work and fun but it is not yet supported by the VME bus system to set the different signals and affect how devices can access each other. It would however be very useful to get the signals visible even if they are disregarded, that would help us to build a working emulation. Currently there are ASIC:s, FPGA:s and TTL/PLA clusters that has been started but not finished to reveal the signals. Also we have no software that relies on the function of these specific signals but the crude address map seems good enough so far.

Last edited by Edstrom; 11/18/21 10:46 AM.

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Edstrom #120078 11/23/21 04:48 PM
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Yeah, I’ve been working on improving the bus emulation, particularly the address map stuff using the new hook system. In my branch, I have an MVME050 SYSCON card that installs itself over the entire VME address space. It acts as a memory bus device of last resort, asserting /VBERR on access after the bus timeout period if no other slot device is overlaying an address. All slot devices pick that up and fire the appropriate callback. This is good enough to get the 120bug firmware to think there’s an 050 available (though I don’t have bus interrupts hooked up yet…)

Last edited by Luigi30; 11/23/21 04:49 PM.
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R. Belmont #120079 11/23/21 04:53 PM
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Yeah, the disk controller I have is an MVME320/A (a 3X805-based scheduler with a WD floppy controller) so that’s what I’d be using. I’ve also got a DRAM expansion board and a Rastergraf TMS34010 video/mouse/keyboard card to add.

Edstrom #120080 11/23/21 05:45 PM
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RG-750?
https://www.ebay.com/itm/184933134736

I've forwarded this thread to a friend that has been hacking on VME 340x0 boards

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