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Edstrom #102681 11/20/15 10:53 AM
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Just a small update on my work on the VME bus. I have used the Nubus and ISA bus drivers as role models and tried to make a top down design based on those but there has been too many bus specifics in those drivers that are irrelevant for the VME bus. So I am doing a revamp of the whole thing and starting from scratch with a bottom up design based on my understandings so far.

The direction I have is to model the VME adress spaces (A16, A24, A32 and A64) independently of the address space of the CPU board and map slot devices into those. This is not nearly enough considering the Address Modifiers (AM) but it is a start. The AM allows to differentiate addresses based on access type like program vs data vs I/O fetches and Non-Privileged vs Supervisory and many more. I guess I have to create a separate address space for each since thay can overlap but I will start with a single fixed one and hope for the best.

I will also consider to use the Besta driver as main candidate since there seems to be a full set of software there to use, adding the SCSI-1 board as the first VME slave board. I am also working on a template VME driver and VME slave board, I may submit those too without include them in the build.


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Edstrom #102720 11/23/15 12:59 PM
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Is it possible to have separate handlers for 8, 16, 32 and 64 bit accesses in the *same* address space. It seems that the memory system will use the first-fit rather than the best-fit, is this correct?

I'd like to trigger VME bus in 4 different addresspaces (A16, A24, A32 and A64) with four different data widths (D8, D16, D32 and D64).

Even an 8 bit CPU can actually trigger any of these through the VME bus device, but usually a 68K like CPU.

Last edited by Edstrom; 11/23/15 01:00 PM.

Because I can
Edstrom #102721 11/23/15 01:18 PM
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Of course you can. Quoting the next.cpp driver:

Code:
static ADDRESS_MAP_START( next_mem, AS_PROGRAM, 32, next_state )
	AM_RANGE(0x00000000, 0x0001ffff) AM_ROM AM_REGION("user1", 0)
	AM_RANGE(0x01000000, 0x0101ffff) AM_ROM AM_REGION("user1", 0)
	AM_RANGE(0x02000000, 0x020001ff) AM_MIRROR(0x300200) AM_READWRITE(dma_ctrl_r, dma_ctrl_w)
	AM_RANGE(0x02004000, 0x020041ff) AM_MIRROR(0x300200) AM_READWRITE(dma_regs_r, dma_regs_w)
	AM_RANGE(0x02006000, 0x0200600f) AM_MIRROR(0x300000) AM_DEVICE8("net", mb8795_device, map, 0xffffffff)


Notice the 32-bit 68030/040 address space has both regular 32-bit handlers and an 8-bit wide Ethernet device. It's not a problem having handlers of multiple widths in one address space.

The 0xffffffff on the 8-bit device is a byte lane mask - in this case, they spent the extra gates so the 8-bit device appears at consecutive byte addresses in the 32-bit address space, but having the 8-bit device appear every 4th byte (in which case the mask would likely be 0x000000ff) is a cheaper, and therefore more common, scenario.

If you mean multiple width handlers at the same *address*, yes, that will blow up in your face.

Edstrom #102724 11/23/15 02:56 PM
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Exactly, the latter has blown up in my face, at least a bit.

So, if I define just one handler for the max width to handle all access types, say a handler for D16 word access at a specific memory range and the CPU accesses it by byte I find that the handler still get a word access.

I want to find out the 'mask' used for that word access to know if it is the even or odd byte that is accessed. Also for D32 of course.

I don't want to map the slot devices in the maincpu address space but in the VME bus adress spaces since the local addresses can differ from the global bus addresses. This makes it difficult for the VME device read/write handler since there is no information about the width. See page 2-12 in the VME bus specification

It is quite common to strap identical slave slot devices to map to different VME adresses OR, a little less common, to different bits on the same VME adress. The latter allows for reading multiple I/O boards in the same VME bus cycle. So even if I leave this special use cases for the future I'd like to prepare the design for it, if possible.


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Edstrom #102725 11/23/15 03:28 PM
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All read/write handlers larger than 8 bits have a mem_mask parameter that indicates the active bus lane(s).

So a 16-bit read to a READ32 handler will be passed a mem_mask of either 0xffff0000 or 0x0000ffff.

Code:
#define DECLARE_WRITE64_MEMBER(name)    void   name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, 
ATTR_UNUSED UINT64 data, ATTR_UNUSED UINT64 mem_mask = U64(0xffffffffffffffff))


Using a separate address space for the bus is fine; that's how we handle the ISA-on-68000 situation that pops up in a few machines we've emulated.

Multiple cards responding to the same read/write is a harder problem, short of actually just passing all reads/writes to all cards (which is obviously not optimal). Olivier, any ideas?

Last edited by R. Belmont; 11/23/15 03:32 PM.
Edstrom #102726 11/23/15 03:49 PM
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Great info, thanks!
I tried do decode all the finer points in the ISA bus implementation but got lost, too much new design patterns to take in I guess and also spread over too many files so I found myself page swapping more than reading code in the end!

smile


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Edstrom #102748 11/24/15 05:36 PM
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Why is A24 an invalid address width? It has special meaning in VME. Should I add it?


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Edstrom #102749 11/24/15 06:09 PM
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Originally Posted By Edstrom
Why is A24 an invalid address width? It has special meaning in VME. Should I add it?


The 68000 only supported 24 bits of address. 68012 (made for HP) had 25 bits. 68020 and beyond were 32 bits.

Al Kossow #102750 11/24/15 06:12 PM
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Originally Posted By Al Kossow
Originally Posted By Edstrom
Why is A24 an invalid address width? It has special meaning in VME. Should I add it?


The 68000 only supported 24 bits of address. 68012 (made for HP) had 25 bits. 68020 and beyond were 32 bits.


checking the spec

Option A24 specifies that all addresses generated by the MASTER or decoded by
the SLAVE will be restricted to no more than 23 bi ts. Option A32 selection
extends the address range to 31 bits. The address modifier lines indicate to
SLAVES whether the address is 15, 23, or 31 bits. Option A32 also requires an
expanded bus system.

Al Kossow #102751 11/24/15 06:24 PM
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Wasn't there also a '68032' which was a 68000-with-all-32-address-pins? I don't know what it was used in nor how many actual package pins it had...

LN


"When life gives you zombies... *CHA-CHIK!* ...you make zombie-ade!"
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