What happens if two devices present data on the data bus at the same time? I think this is what happens here in the Esselte 100 keyboard i/o design and I am trying to figure out how to get the right result our from the operation. Presumably a low dataline sinks a high dataline so I get a kind of fast scan?
The circuit diagram has two PIA:s on the same chip select S1 which is the Y1 output from a 74138 when (A15=1, A14=1, A13=0, A12=0, A11=1) in the C8xx adress space. The neat detail is that the first PIA is selected by A4 and the second by A3, on PIA pin 22, which means both can be addressed at the same time! This makes sense for writes setting up both PIA:s with the same data driven by the CPU. But how will a read work when the 6820 PIA:s drives the bus and is it/can it be supported by MAME?
Indeed the ROM uses this feature accessing the following adresses at startup:
The documented memory map says PIA1 is at C808-C80b and PIA2 at C810-C813 so I was puzzled by this startup code. Appreciate some insights on this.