Home Page Forums MAME MAME TMS-09xx/1xxx thread (was New Dumps)

The PLAs look ok on the 0972?
- microinstructions to the left of the ROM
- main opcode redirectionm at mid-top of die
- output pla at left of die

The Mr.Challenger VSM, what was the pinout like?
Is a newer TMS6125 you have (for example Touch n Tell) the same pinout?
I want to make MAME TMS6100 emulation more accurate. The current one is from 2010. That was before we added Speak & Spell driver.

*edit* RCK I think is a gate/mask to CLK, maybe this was the thing you were having trouble with when reading it out.

Another VSM question. On Mrchal. the game reads from VSM when M0 is high. This implies the DATA lines are ready for reading after rising edge of READ command. Our current emulation model assumes DATA can be read after _falling_ edge of READ cmd.

Are you able to confirm this? And is it the same way on other VSMs?

Checked touch and tell pcb with meter, conclusion is the tms6125 datasheet (1) is right, despite what I've been told by others.
See https://www.dropbox.com/s/e9rrrq9h8t75zcx/2015-12-29%2014.42.43.jpg?dl=0
You can see the tms6100 footprint with the flashlight shining thru the pcb and the tms6125 above that. Pin 1 of both footprints is at the bottom left of each one. note the /CS and VSS of the tms6100 footprint are tied together by a trace.

Also note the 'top row' (pins 15-28) of the tms6100 are n/c inside the package, so ti used that whole row of vias as convenient tie points, they don't actually do anything to the 6100.

BUT. one new thing jumped out at me:
Pin 2 of the tms6100 has a trace connected to it. The tms6100.cpp lists this pin as N/C, and the other end of the trace connects to CD2802 pin 2, the PDC pin. Maybe some early tms6100s required a PDC pulse on pin 2 to accept m0/m1 commands? Or perhaps it was a routing error at TI where someone mixed up pin 2 of cd2802 and pin 2 (which is supposed to be N/C?) on the tms6100 when laying out the board.

LN

Simply cut pin 2 and see if it still works?
I wouldn't be surprised if pin 2 is the optional RCK pin.

Well, the touch and tell is dismantled (i only have the board for it) so i can't cut it. Also the touch and tell doesn't use tms6100 roms except in cartridges. The rare Vocaid does use a tms6100, though.

LN

Unfortunately, the 0972 PLAs are gone. Well, they are embedded in plastic, torn off the die. I might be able to get them out when it gets warmer. The 0952 die is laid out like the TMS1000: www.seanriddle.com/0952_metal.jpg

I am sure that the Mr Challenger CD2601 pinout is #2 that you listed above. The PCB connects pins 4 to 6, and 7 to 10. But I dumped it using pin 4 for data/addr 8 and pin 10 for M1. I tried using 6 for data/addr 8 and got nothing on that pin. I also had to just tie CLK high, instead of clocking it. The chip is marked TMC0355BNL P CD2601 DCU 8035.

I've got a Super Stumpers 7-8 Word Module that had a 28SDIP TMS6100 that I dumped and verified the same as listed on LN's page. Only pins 1-14 were soldered in; the other 14 didn't even go through holes in the PCB- pins 1-14 were bent to allow it to fit. It also has unused holes for a 16-pin chip. Nothing is marked on the PCB, but the wiring matches your TMS6125 pinout #1 above.

I did not electronically dump the Touch n Tell VSM; I decapped it. So I can't verify how to dump it. The chip was marked CD2610NL MBDW 8922 and the die is marked T0355D 2610B. The Touch n Tell PCB also has pads for a TMS6100 SDIP28, and it is connected to the TMS6125 DIP16 pads similarly to the Super Stumpers Word Module.

So it looks like there were two TMC0355 pinouts.

I've read all VSMs with M0 low. On Mr Challenger, it doesn't look to me like the data is valid until after M0 goes low, but I'm looking at exported data- I didn't save a Logic capture for some reason. I'll set it up again and check.

See Mr. Challenger patent pdf page 45, source code says:

set R12 (is CS)
set R6 (is M0)
wait
read K
reset R6
<-- I assume DATA is still readable here too
reset R12

If I do a quick hack in tms6100.cpp(MAME), the jingles and beeps work fine in the game. Otherwise sound is buggy.

Thanks for confirming I'm not crazy

Well, remember, the bus on the tms6100 (like the ctrl bus on the tms5100) is bidirectional but needs one cycle to switch states. I assume a load address command switches it to input, an idle command does nothing (prev state remains), a read bit command switches it to output, and read and branch may do nothing and leave the state alone, not clear. The PLA in the speak and spell patent (US4189779 pdf pages 42-52, i.e. figures 19, 20 and 21, see http://www.pat2pdf.org/patents/pat4189779.pdf or https://www.google.com/patents/US4189779 ) explains when the state switches, I think?

LN