Home Page Forums MAME MAME TMS-09xx/1xxx thread (was New Dumps)

Yeah, they must have done those changes to optimize on some calculation loops (the extra microinstruction on on of the branch opcodes for example too)

FWIW here's another one with many changes over the standard instruction set. TMS1100 Touch N Tell: http://pastebin.com/7XRvyvt5
*edit* woops, that note for opcode 04 is a2aa, not a4aa.

I posted info on the Speak & Spell Compact: www.seanriddle.com/snscompact.html

My scans https://imageshack.com/a/WKl4

Clearly the EVA11 has a TMS MCU
But the EVA24 doesn't or I'm blind. the B8416 is a RAM chip apparently. The missing chip is of course the VSM, which I unsolder in the vid..

Are schematics for snspell compact available? If not, I don't expect trouble emulating it, so there's no need to trace the pins for now.

FWIW note the only difference between 8012 and 8011 opcodes is that 8012(tntell) adds IYC microinstruction to RSTR. The rest is same as my pastebin above.

The S/B8416 chip is the mcu, its a national semiconductor ('natsemi') chip of some sort, note the logo: http://www.elnec.com/ic_logos/national_f.gif

LN

Yeah I know its NS, but all hits pointed to some ram. You are probably right, which makes this interesting. Why switch to an NS mcu?

I did trace the pins, but haven't double-checked everything. I'll type it up and let you know. It does look pretty standard.

Not sure. I'm guessing it is a COP400 series mcu, which means it should be dumpable without decap using a debug mode.

It could also (unlikely) be an INS 807x SC/MP-3 with 4k of rom, but I seriously doubt it.

LN

Seems it's same as tntell:
// R10: TMS5100 PDC pin
// R9: power-off request, on falling edge
// R0-R8: input mux

// K: multiplexed inputs
// K4: TMS5100 CTL1

// O3210: TMS5100 CTL8124
I see O4 and O5 on the output PLA too, they're not connected?


BTW David do you want credit in MAME whatsnew? I'll put in anondumper for now.

If its stuff I talk about publicly in this forum, then plgDavid (David Viens) is fine! Thanks!