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It's shown as connected directly to ground and thus in active state (as it's an active low pin).

Edit: Here's the schematic page. There's no rs232 voltages involved, it's all TTL 0-5V stuff.

I recall a TEST/LOOPBACK circuit in 8088 (port 0x0A). It was discussed in

http://forums.bannister.org/ubbthreads.php?ubb=showflat&Number=103331&page=20#number95139

- but it is not implemented in our present source (Git).

Bit 5 redirects one output to another input during inital tests, and is unique to the Rainbow.

In my understanding, serial, printer and keyboard are tested in one large loop, so that interfaces must be fully functional (and redirectable by bit 5). As things stand now, this is not the case (else errors 40 and 60 for serial/printer would be absent at boot time).

Another indication: 8088 registers 0x02, 0x06, 0x0e are not implemented in 'rainbow.cpp' (unless i missed a super secret fork).

@R.Belmont: please forgive my stubbornness



(CLICK TO ENLARGE IMAGE; circuit in upper left corner)

Tell you what, since Bitsavers is a public website, how about you send us a link to what's in the address bar of that barely-readable screenshot?

Here you go: page 17

Here's where I'm at WRT the floppy.

First line 2010 should have the logic reversed force_read set is true. That changes error 12 - not read to 28 - rx50 board failure. That error is caused here. The head load line is shown in the schematic here but you can see on the next page it isn't pushed out to the drive. Page 3 seems to show that the motor for the selected drive is enabled implicitly by the head load line going high. The question I have though is what is happening with the Z80 though. I'd guess that the head load status bit on the 1793 isn't being set until the motor is up to speed (which would be reflected by the ready line if it weren't forced high on line 274 of the disassembly) which is possible as that bit is the HLD line anded with HLT, but the schematic doesn't seem to reflect that.

Thanks for sorting out the Rainbow driver
Sorry, i dont have deep links on Bitsavers for you.

(see circuit at bottom of screenshot)
https://dl.dropboxusercontent.com/u/37819653/BANNISTER/HLD%20-%20HLT%20-%20MOTOR%20ON.jpg

Source: Field Maintenance Print Set / MP-01722-01 from 1984 where the schematics of the RX50 controller can be found (scroll to end of document).

https://archive.org/details/bitsavers_decrainbowwSchematicJul84_3508632

Page 231 of the OCR version of Rainbow Technical Manual (pc100tm1_text) explains how the Head Load Circuit works -

- Disk present in the selected drive and the door is closed (DISK P H)
- drive is selected and the spindle motor is turned on (MPWR SEL H)

From the RX-50 Dual _Diskette Drive_ Specs:

Head settling time: 30 ms (maximum value)
Head load time: 30 ms (maximum value)

Source : QV069-GZ 100+ 100B Technical Documentation Apr85

That's about it all i could find.

z80 arbitrator prom is dumped now, so we should now have absolutely everything we need to fully emulate this.

P.S. I notice during bootup that it displays all character sets on the top 2 rows of the screen for a bit before erroring out. Is it trying to read the character set rom using the diagnostic loopback stuff?

LN

Nope, the displayed errors are for the serial port loopback - the POST doesn't do the bit-serial video reading.

So, here's what the two loopback bits do, explained in a table:
inputs:
CommRxD = EIA/RS232 uart receive pin
PRTRxD = printer uart receive pin
KBDRxD = keyboard data uart? receive pin
VidCLK = DC011 video asic clock
PRTCLK = printer uart serial clock for rx/tx

signals:
CommRCV = EIA/RS232 port rx pin (after going through mc1489?)
CommTxD = EIA/RS232 uart transmit pin
PRTRCV = printer port db25 rx pin (after going through mc1489?)
KBDTxD = keyboard data uart? transmit pin
KBDRCV = keyboard data rj11 jack receive pin
PRTTxD = printer uart transmit pin
MASCLK = master (and video) clock
500Khz = 500Khz clock
PRTRxTxC = printer baud clock (configurable)
250Khz = 250Khz clock

EDIT: The state of the two loopback pins (as well as the nvram 'program' and 'recall' bits, and the 'reset' bit) can be read back from the i/o register 0x6 as well as written. oddly, the schematic seems to show that the bit order is reversed between read and write, but this could be a drafting error on the schematic. Three bits are write only, when read back they read as a constant set by 3 jumpers on the board.

LN

Jumpers are emulated - and available from the 'DIP switches' GUI as W13,W14 and W15. Judging from the ROM code the 3 bits were used to branch into factory test code at boot time (and elsewhere).

https://github.com/shattered/retro-...ow100b/8086_DISASSEMBLY_23-022e5-00#L747

As most jumpers drastically alter the code flow i havent found a practical use yet (except for folks able to write custom BOOT ROMs).

P.S.: i would not bother too much about the tests at boot time, now the keyboard showstopper is gone (see latest Github entries).

RX50 diagnostic test disk offers more unsettling insights (floppy 'individual test' claims that SEEK_WITH_VERIFY is broken etc.) Possible fixes there could also help TRS-80 users, see WD 1793 problems described by Robbert