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Joined: May 2012
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iscsi/floppy PR sent -- https://github.com/mamedev/mame/pull/1641How to demo: attach a 720K floppy image to drive 0, wait for selftests to pass and enter debugger:
; configure unit 0 as QD floppy (80 tracks, 2 sides, 9 spt)
do b@2300=2
do b@2301=50
do b@2302=9
do b@2303=0
do b@2304=2
do b@2305=1
do b@2306=ee
do b@2307=0
do b@2308=1
; equivalent:
do q@2300=25009000201ee00
do b@2308=1
do d@2104=2300
do w@210c=0
; target 7, command 0x0a
do w@2100=e0a
; read lbn 0 -- data will be at 0x4000 in memory
do w@2102=1
do d@2104=0
do d@2108=4000
do w@210c=0
do w@2100=e20
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Joined: Aug 2015
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OP
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I saw you enabled the SCSI stuff too, would be cool to do the same thing with a HDD! or is there a boot able floppy for Force CPU30 out there?
Because I can
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SCSI stuff won't work until NCR5385E/NCR5386 device is written -- I've only added a stub to make self-test pass  Yes, there is a floppy (from Linux/Besta port) -- two, in fact: flop800.* on http://ftp.stu.neva.ru/besta/linux-bin/But neither is designed for CPU30R4 -- one is for 'CP31' board (could be an earlier revision of CPU30) and another for 'HCPU30'.
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Ok, it is on my list to add all the variants of the boards too, should be pretty stright forward I think. The CPU30 has a floppy controller too on P2 connecor, not sure about the CPU-31 one though. I wonder if the besta floppy will boot.
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far as I can see from the docs, the non-Force boards are
cp31 = cp30 + rtc
68030, 68882 @ 33 MHz
68153 BIM $FF800800
68230 PIT $FF800C00
68561 MPCC $FF800000
62421 RTC $FF800A00
Centronics $ff800200 ???
:
32KB 0ws SRAM $FF04xxxx..$FF07xxxx
256KB EPROM $FF00xxxx..$FF03xxxx
:
MPCC #2, #3 $ff800200, $0xff800600 optional, on SRAM daugtherboards
cp33 =
68030, 68882 @ 25 or 33 MHz
EPROM -- 512KB, 1MB or 2MB
DRAM -- up to 64MB
:
console MPCC $FF800000 only in prototypes, later models move console to 2681
68153 BIM $FF800800
68230 PIT $FF800C00
62421 RTC $FF800A00
WD33C93A SCSI $FF801000 & $FF810000 (dma)
i82077 FDC $FF801200
CENC (parallel) $FF800200
SCN2681 $FF801400
IRQRG $FF801600
Am7990 LANCE $FF820000
hcpu30 =
68030, 68882 @ 33 MHz
68020 -- I/O cpu
:
DRAM -- 4 or 16 MB
PROM -- up to 64 KB
SRAM -- 8 KB non-volatile or 32 KB volatile
:
2xRS232/RS422 $FFFF8120, $FFFF8140
SCSI $FFFF8160
Floppy $FFFF8260
Centronics $FFFF8280
RTC $FFFF8100
Ethernet $FFFF82A0
Linux port supports CP20, CP30, CP31 and HCPU. Don't know what SysV supports -- there are boot floppies for that, too.
Last edited by shattered; 11/06/16 09:56 PM.
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Great, I will try booting one of the Linux floppy images on a CPU-30 when I get there. Right now I am swearing because I just found out that the poor CPU-40 init code I pointed out is even worse, it seem that the PIT and the DUSCC gets the *same* init sequence. This indicates that some table driven init assumes something I don't reflect at the moment, such as a proper board ID or relocated devices, need to dig deeper before the CPU-40 board will start producing any output. The FGA-002 is updated too since the new init is 4.x vs 3.x for the CPU-30 and there are a lot of new registers. I need to park that for a moment, thought it would be easy!
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The CPU-25 has a Rockwell 68561 MPCC chip. Considering the huge register layout difference to the Signetics 68562 DUSCC used on later Force products I am quite sure an ignorant purchaser made a great deal with Signetics thinking that the difference should be small, which it is on a feature lavel. Software guys must have cried for weeks..
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Joined: May 2012
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Who knows... It's been a while since I've seen a working Besta, so can't check what's actually installed; chips on this board may have been replaced after it was pulled (notice there's no CPU )
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Joined: Dec 2015
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The CPU-30's RTC72423 could probably just use the existing MSM6242 device. Epson's RTC72421 (DIP) and RTC72423 (SOP) seem to be mostly pin-compatible with the RTC62421 and RTC62423 mentioned in the device file, with the only difference being the lack of an external XTAL hookup.
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