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Joined: Mar 2001
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Rainbow's almost done RS-232 wise, you just need to hook up the transmit from the uPD7201. Find this:
MCFG_UPD7201_ADD("upd7201", XTAL_2_5MHz, 0, 0, 0, 0) // 2.5 Mhz from schematics
MCFG_Z80DART_OUT_INT_CB(WRITELINE(rainbow_state, mpsc_irq))
Add these two lines:
MCFG_Z80DART_OUT_TXDA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_txd))
MCFG_Z80DART_OUT_TXDB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_txd))
And that will enable the Rainbow to transmit on both RS-232 ports.
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Joined: Aug 2015
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Or you can try the new z80sio where I have added the upd7201 support recently, or did I ask you to do that already? 
#include "machine/z80sio.h" // instead of z80dart.h
MCFG_UPD7201_ADD("upd7201", XTAL_2_5MHz, 0, 0, 0, 0) // 2.5 Mhz from schematics
MCFG_Z80SIO_OUT_INT_CB(WRITELINE(rainbow_state, mpsc_irq))
MCFG_Z80SIO_OUT_TXDA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_txd))
MCFG_Z80SIO_OUT_TXDB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_txd))
Because I can
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Joined: Mar 2001
Posts: 17,215 Likes: 234
Very Senior Member
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The hooks back to the 7201 would need to be changed for the two RS-232 ports too then
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Joined: Apr 2012
Posts: 193
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DTR and RTS output seem to be controlled entirely by the 808x (with some help by the BIOS). I have no idea how to reconcile that with the Z80DART (or Z80SIO) code. Is it possible the CPU controls these lines independently? Additionally, the status of the RI, CTS and DSR lines have to be reflected on 808x port 02 ('comm_control_r' in Rainbow.cpp). Tony Duell's schematics and the 2 stubs we have in RAINBOW.CPP - Tony Duell's schematics vs. curent code (right)As always, i could hack my way to success (e.g. patch Windows 1.0.3 to not use the hardware flow control for mouse detection). I better ask and do it 'the MAME way' (darn macros). Something i can do independently: the serial mouse needs a downgrade to mimic the old MS 2 button mouse protocol ("M" response, no third button, possibly 7 O 1 instead of 7 N 1). Again, thanks for any hints History would be different if DEC officials had recognized the potential of Windows on their non compatible machine. GRAPH application on MS Windows 1.0.4 (Rainbow 100 - MESS)
Last edited by Bavarese; 07/14/17 11:08 AM.
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Joined: May 2004
Posts: 996 Likes: 103
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DTR and RTS output seem to be controlled entirely by the 808x (with some help by the BIOS). I have no idea how to reconcile that with the Z80DART (or Z80SIO) code. Is it possible the CPU controls these lines independently? Additionally, the status of the RI, CTS and DSR lines have to be reflected on 808x port 02 ('comm_control_r' in Rainbow.cpp). Tony Duell's schematics and the 2 stubs we have in RAINBOW.CPP - Tony Duell's schematics vs. curent code (right)Something like this? https://git.redump.net/mame/tree/src/mame/drivers/cgenie.cpp#n240
READ8_MEMBER( cgenie_state::control_r )
{
uint8_t data = 0;
data |= m_cassette->input() > 0 ? 1 : 0;
data |= m_rs232_rx << 1;
data |= m_rs232_dcd << 2;
return data;
}
You just need to save the line state from the rs232 device and then return it in the appropriate location.
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Joined: Mar 2001
Posts: 17,215 Likes: 234
Very Senior Member
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Very Senior Member
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Posts: 17,215 Likes: 234 |
Windows itself will program the 7201 for 7O1 or whatever format, and I think our serial mouse supports the old protocol because we've used it with PC Windows 1.0.x.
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Joined: Apr 2012
Posts: 193
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Posts: 193 |
I have rewritten the Rainbow driver to use Z80SIO instead of Z80DART as well as hardware flow control. Now at least, the mouse resets (ser_mouse.cpp -> routine: input_rts). https://www.dropbox.com/s/6ya3qj96f0k6rax/Z80SIO_with_MS_MOUSE_-_Windows_1.x.jpg?dl=0Then, unexpected bytes appear. Instead of the expected identifier ($4D = "M") i observe $3b (binary 0111011). Parameters are 7,N,1, 1200 baud (set by Windows at startup for both directions). Is my code correct? https://www.dropbox.com/s/so2vyytgkcz8azl/2017%2007%2016%20-%20rainbow.cpp?dl=0Routines and statements added: READ8_MEMBER(rainbow_state::comm_control_r) WRITE8_MEMBER(rainbow_state::comm_control_w) WRITE_LINE_MEMBER( rainbow_state::rs232_dcd_w ) WRITE_LINE_MEMBER( rainbow_state::rs232_dsr_w ) WRITE_LINE_MEMBER( rainbow_state::rs232_cts_w ) WRITE_LINE_MEMBER( rainbow_state::rs232_ri_w ) MCFG_RS232_DCD_HANDLER(WRITELINE(rainbow_state, rs232_dcd_w)) MCFG_RS232_DSR_HANDLER(WRITELINE(rainbow_state, rs232_dsr_w)) MCFG_RS232_CTS_HANDLER(WRITELINE(rainbow_state, rs232_cts_w)) MCFG_RS232_RI_HANDLER(WRITELINE(rainbow_state, rs232_ri_w)) I can also provide a ready-made CHD with Windows 1.x if somebody wants to test drive. Thanks for having a look.
Last edited by Bavarese; 07/16/17 07:28 PM.
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Joined: Aug 2015
Posts: 406
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I can't really tell if it is correct for the Rainbow as I don't know that machine but it looks ok. If you turn on logging in z80sio.cpp by setting some of the LOG bits then you'll see what's going on, I'll suggest you use
#define VERBOSE (LOG_SETUP|LOG_INT|LOG_CMD|LOG_DCD|LOG_CTS|LOG_TX|LOG_RX|LOG_GENERAL)
#define LOG_OUTPUT_FUNC printf
You can remove LOG bits if it gets too cluttered. For instance you will see the baudrate as seen by the 7201 and you will see special commands such as software iacks. The LOG_OUTPUT_FUNC directs the output to your terminal so you can use more, less or grep on the log or just direct it to a file, quite handy compared to the MAME log window The call to m1_r() on line 2571 is not needed as the 7201 does not have an M1 input, instead it expects to get a software iack.
Because I can
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Joined: Apr 2012
Posts: 193
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Joined: Apr 2012
Posts: 193 |
Thanks for the nudge in the right direction. I now see a lot of lines with "Null command" and "CRC_RESET_NULL". https://www.dropbox.com/s/6ss4f4g1d0mtlhe/Null_command.png?dl=0Stop bits, length (7), parity (none) seem to be correctly set. What is totally absent -in the log- are RX and TX baud rates (at least values do not appear in 'update_serial'). Here the code section where i set an external baud rate generator from within Rainbow.cpp (2nd screenshot). It uses the Com8116 baud rate generator Shattered recommended (#include "machine/com8116.h") -
// PORT 0x06 : Communication bit rates (see page 21 of PC 100 SPEC)
WRITE8_MEMBER(rainbow_state::comm_bitrate_w)
{
m_dbrg_A->str_w(data & 0x0f); // PDF is wrong, low nibble is RECEIVE clock (verified in SETUP).
printf("\n(COMM.) receive bitrate = %d ($%02x)\n", comm_rates[data & 0x0f] , data & 0x0f);
m_dbrg_A->stt_w( ((data & 0xf0) >> 4) );
printf("(COMM.) transmit bitrate = %d ($%02x)\n", comm_rates[((data & 0xf0) >> 4)] ,(data & 0xf0) >> 4);
}
// PORT 0x0e : Printer bit rates
WRITE8_MEMBER(rainbow_state::printer_bitrate_w)
{
m_dbrg_B->str_w(data & 7); // bits 0 - 2
m_dbrg_B->stt_w(data & 7); // TX and RX rate cannot be programmed independently.
printf("\n(PRINTER) receive = transmit bitrate: %d ($%02x)", 9600 / ( 1 << (7 - (data & 7))) , data & 7);
// "bit 3 controls the communications port clock (RxC,TxC). External clock when 1, internal when 0"
printf(" - CLOCK (0 = internal): %02x", data & 8);
}
Maybe something is missing? There is also an odd clock bit (not part of the Z80SIO, must be external circuitry) not handled yet (normally zero). See printer_bitrate_w above. Log from screenshot (as text):
Z80SIO ":upd7201_new" Channel B : CRC_RESET_NULL
* :upd7201_new:chb B Reg 02 <- 00 - WR2
void z80sio_channel::control_write(uint8_t)(00) reg 02
Z80SIO ":upd7201_new" Channel B : Interrupt Vector 00
(COMM.) receive bitrate = 1200 ($08)
(COMM.) transmit bitrate = 1800 ($09)
void z80sio_channel::control_write(uint8_t)(02) reg 00
void z80sio_channel::do_sioreg_wr0(uint8_t) :upd7201_new:cha Ch:A : Null command
void z80sio_channel::do_sioreg_wr0_resets(uint8_t) :upd7201_new:cha
Z80SIO ":upd7201_new" Channel A : CRC_RESET_NULL
* :upd7201_new:cha A Reg 02 <- 10 - WR2
void z80sio_channel::control_write(uint8_t)(10) reg 02
Z80SIO ":upd7201_new" Channel A : Interrupt Vector 10
void z80sio_channel::control_write(uint8_t)(04) reg 00
void z80sio_channel::do_sioreg_wr0(uint8_t) :upd7201_new:cha Ch:A : Null command
void z80sio_channel::do_sioreg_wr0_resets(uint8_t) :upd7201_new:cha
Z80SIO ":upd7201_new" Channel A : CRC_RESET_NULL
* :upd7201_new:cha A Reg 04 <- 44 - WR4 - Async Clock, Parity and stop bits
void z80sio_channel::control_write(uint8_t)(44) reg 04
Z80SIO ":upd7201_new" Channel A : Parity Enable 0
Z80SIO ":upd7201_new" Channel A : Parity Odd
device_serial_interface::stop_bits_t z80sio_channel::get_stop_bits() :upd7201_ne
w:cha
1 STOP BIT.Z80SIO ":upd7201_new" Channel A : Stop Bits 1
Z80SIO ":upd7201_new" Channel A : Clock Mode 16X
int z80sio_channel::get_rx_word_length() :upd7201_new:cha
Z80 SIO) receive word length: 07device_serial_interface::stop_bits_t z80sio_chan
nel::get_stop_bits() :upd7201_new:cha
1 STOP BIT.void z80sio_channel::update_serial()
(Z80SIO) : data_frame (data_bit_count = 07), parity = 00, stop_bits = 01
void z80sio_channel::control_write(uint8_t)(03) reg 00
void z80sio_channel::do_sioreg_wr0(uint8_t) :upd7201_new:cha Ch:A : Null command
void z80sio_channel::do_sioreg_wr0_resets(uint8_t) :upd7201_new:cha
Z80SIO ":upd7201_new" Channel A : CRC_RESET_NULL
* :upd7201_new:cha A Reg 03 <- 41 - WR3 - Async Rx setup
void z80sio_channel::control_write(uint8_t)(41) reg 03
Z80SIO ":upd7201_new" Channel A : Receiver Enable 1
Z80SIO ":upd7201_new" Channel A : Auto Enables 0
int z80sio_channel::get_rx_word_length() :upd7201_new:cha
Z80 SIO) receive word length: 07Z80SIO ":upd7201_new" Channel A : Receiver Bits/
Character 7
int z80sio_channel::get_rx_word_length() :upd7201_new:cha
Z80 SIO) receive word length: 07device_serial_interface::stop_bits_t z80sio_chan
nel::get_stop_bits() :upd7201_new:cha
1 STOP BIT.void z80sio_channel::update_serial()
(Z80SIO) : data_frame (data_bit_count = 07), parity = 00, stop_bits = 01
void z80sio_channel::control_write(uint8_t)(05) reg 00
void z80sio_channel::do_sioreg_wr0(uint8_t) :upd7201_new:cha Ch:A : Null command
void z80sio_channel::do_sioreg_wr0_resets(uint8_t) :upd7201_new:cha
Z80SIO ":upd7201_new" Channel A : CRC_RESET_NULL
* :upd7201_new:cha A Reg 05 <- 28 - WR5 - Async Tx setup
void z80sio_channel::control_write(uint8_t)(28) reg 05
Z80SIO ":upd7201_new" Channel A : Transmitter Enable 1
int z80sio_channel::get_tx_word_length() :upd7201_new:cha
Z80 SIO) transmit word length: 07Z80SIO ":upd7201_new" Channel A : Transmitter B
its/Character 7
Z80SIO ":upd7201_new" Channel A : Send Break 0
Z80SIO ":upd7201_new" Channel A : Request to Send 0
Z80SIO ":upd7201_new" Channel A : Data Terminal Ready 0
int z80sio_channel::get_rx_word_length() :upd7201_new:cha
Z80 SIO) receive word length: 07device_serial_interface::stop_bits_t z80sio_chan
nel::get_stop_bits() :upd7201_new:cha
1 STOP BIT.void z80sio_channel::update_serial()
(Z80SIO) : data_frame (data_bit_count = 07), parity = 00, stop_bits = 01void z80
sio_channel::update_rts()() ":upd7201_new" Channel A
void z80sio_channel::set_dtr(int)(1)
Last edited by Bavarese; 07/17/17 12:33 PM.
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Posts: 406 |
It looks like the SIO is expecting to get a clock that is 16x the actual bit rate here:
Z80SIO ":upd7201_new" Channel A : Clock Mode 16X
Are you sure the BRG is producing the right bitrate? Also remember that you need two call to, for instance, rxca to shift one bit into the SIO, as only every second is a raising flank, given that you only call it when the clock changes state.
Because I can
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