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Re: Fairlight CMI [Re: SynaMax] #112893
03/17/18 02:06 AM
03/17/18 02:06 AM
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R. Belmont Online content
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No, the 6850 and 6551 are very different and definitely not compatible. That's probably your regression right there.

Last edited by R. Belmont; 03/17/18 02:07 AM.
Re: Fairlight CMI [Re: SynaMax] #112895
03/17/18 05:24 AM
03/17/18 05:24 AM
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Just Desserts Offline
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No offense, but SynaMax and RB, I'm not a grotesque moron. That's probably not the regression.

SynaMax, I would ask that you look at CMI2xServiceManual.pdf, particularly page 205 of 378 in the PDF. It should be the schematic page for "Q133-02, Sheet 3 of 5".

If you look closely at it, you'll note a gang of four chips, all of which are marked on the schematic, surprise surprise, as "6551". They should be mapped in the correct place and hooked up correctly in the memory map. There may be lurking bugs, but I assure you, I'm not so colossally stupid that I would arbitrarily utilize the MOS 6551 ACIA in place of the Motorola 6850 ACIA.

Re: Fairlight CMI [Re: Just Desserts] #112897
03/17/18 09:48 AM
03/17/18 09:48 AM
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SynaMax Offline OP
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Sorry, I apologize if I came off as rude or implied that you were stupid in my previous post; I assure you that was not my intent.

Thanks for the heads up on the 6551, I can't believe I missed that. I had my service manual open the whole time and I checked to see if the 6551 was on there or not. My bad.

Re: Fairlight CMI [Re: SynaMax] #112898
03/17/18 11:16 AM
03/17/18 11:16 AM
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I have been following this thread out of curiosity, and have also compared Phil's original code with the current but not noticed any obvious regressions. Have you tried enabling trace on each CPU? This should allow you to compare both old and new traces to see where they diverge.


BBC Model B, ATPL Sidewise, Acorn Speech, 2xWatford Floppy Drives, AMX Mouse, Viglen case, etc.
Re: Fairlight CMI [Re: Pernod] #112910
03/19/18 07:53 PM
03/19/18 07:53 PM
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SynaMax Offline OP
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Thanks a lot for the suggestion, Pernod! As a beginner when it comes to debugging, I really appreciate it. smile

I did a trace and compared the first CPU between the two emulations. I'll post my findings, once I figure out what's the subroutines are doing.

Re: Fairlight CMI [Re: SynaMax] #112929
03/21/18 07:47 AM
03/21/18 07:47 AM
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SynaMax Offline OP
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So I found something wrong with the register for the Floppy Disk Controller on CPU2.

The instruction at $DDD9 loads into register A the byte from $FCE1 (which is the status and address register for the FDC). In MESS, this byte switches to C8 and the next instruction checks this with a BITA instruction (BITA #$40). If the result equals to 40, it proceeds with the subroutine and continues loading data from the floppy. Looking at the memory window in MAME, I don't see $FCE1 change at all; it's always 00. The debugger does say the byte is being read and written to, but it hits a point where instead of register A having the value C8, it just stays at 88 and since it fails the BITA instruction, it stays in a loop and constantly goes back to $DDD9. Eventually it gets out of the loop but nevertheless, I don't believe this to be the expected behavior.

As for CPU1, things start going wrong at instruction $FB36. The opcode there is LDB $1,X. X's value at this point is FC84, which means it's an ACIA register. In MESS, it seems that the value at $FC85 is always 00. That's what shows in both the memory window as well as the B register. In MAME, the ACIA registers are all FF (however, the value that's loaded into the B register is 60; could someone explain why that is?). This instruction gets called quite frequently and since the register values are different, instructions $FB3C and $FBE3 get skipped a lot in MAME.

Instruction $F8EE (TST $FE00) is very important for loading the system disk. It tests the byte at $FE00 to see if it's a 1 or 0. If it's a 1, it proceeds to instruction $F8FD, where it uses jump offsets located at $FE01 to boot the system.

Setting up a watchpoint at $FE01 reveals these jump addresses:

F815
0EEA
8CBF
8C7F
8C9B
8CFD
1C31

Everytime a new address is written to memory, $FE00 changes to a 1 so that the program can go fetch the new address. In MAME, $1C31 is never reached because after $8CFD, the $FE00 byte stays on.

I'm still double checking to make sure I'm not missing anything else, but I'm pretty confident the problem lies in the ACIA (or at least it's a good place to start).

Re: Fairlight CMI [Re: SynaMax] #112930
03/21/18 12:59 PM
03/21/18 12:59 PM
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Originally Posted by SynaMax
In MESS, this byte switches to C8 and the next instruction checks this with a BITA instruction (BITA #$40). If the result equals to 40, it proceeds with the subroutine and continues loading data from the floppy. Looking at the memory window in MAME, I don't see $FCE1 change at all; it's always 00.

The fdc_r function has an (apparently unneeded?) machine().side_effects_disabled() at the start so the debugger won't show you the real value. Bit 6 is the interrupt line so it's not getting a expected irq from the fdc. Also the motor control seems to be missing which would cause problems (or does the 1791 have a builtin motor control?). Edit: It's an 8" drive so the motor is always on.

Last edited by crazyc; 03/21/18 01:59 PM.
Re: Fairlight CMI [Re: SynaMax] #112967
03/27/18 06:58 AM
03/27/18 06:58 AM
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I think that i8214 emulation should call check_interrupt() in etlg_w() and inte_w() -- this solves most of screen corruption in ms6102 (8275 sometimes happens to set IRQ while INTE=0 in 8214, so interrupt is ignored and never handled.)

Doesn't help CMI, though.

Re: Fairlight CMI [Re: SynaMax] #112968
03/27/18 01:20 PM
03/27/18 01:20 PM
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shattered: that makes sense, go ahead and submit it.

Re: Fairlight CMI [Re: SynaMax] #112970
03/27/18 10:17 PM
03/27/18 10:17 PM
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SynaMax Offline OP
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Something weird happens on CPU 1 at instruction $8D22.

In MESS, this is what happens:

Code
PC = 8D22 S = 0F00 CC = D8 DP = 00 A = FF B = 80 D = FF80 X = 7DF0 Y = 9110 U = C800

8D22: ANDCC #$EF          // logical AND EF with D8 in CC register 
8D24: LDX   #$1C31        // load 1C31 into X, CC = C8
8D27: STX   $FE01         // store 1C31 at FE01
...


As you can see this writes the important jump address 1C31 at offset FE01.

In MAME, this happens:

Code
8D22: ANDCC #$EF          // logical AND EF with D8 in CC register 
4FE2: LDA   #$40          // why did it jump to 4FE2?  CC register is still D8.
4FE4: LDX   #$7B8C
4FE7: JMP   $4FF2
4FF2: CLRB  
4FF3: TFR   B,DP
4FF5: JSR   $4DCC
4DCC: CLR   $FCFC
4DCF: INC   $1CE2
4DD2: RTS   
...


I double checked the CPU flags at $8D22 in both MESS and MAME and they're the same: EF.IN...

The only thing that changes when 8D22 jumps to 4FE2 is the PC pointer (obviously) and the stack, which goes from 0F00 to 0EF4; CC doesn't change at all. From there on MAME just continues running the wrong instructions (looks like it loops from 4FE2 to 5025), writing to channel card 6 and spamming the command prompt.

Last edited by SynaMax; 03/27/18 10:29 PM.
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