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#119931 10/28/21 09:28 AM
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PhillHS Offline OP
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Hi all,

Is there an easy way of inserting a short delay? I could setup an emu_timer, set a flag variable and then clear it in the timer's handler. then have a while (flag) do {} in the mainline.
But is there an easier way of doing this?

Cheers.

Phill.

PhillHS #119932 10/28/21 11:45 AM
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That's not how MAME works. The while loop would prevent time from advancing. What are you actually trying to do?

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PhillHS Offline OP
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Insert a delay between the CPU writing a value to a periperal and the value actually being written to the periperal.

e.g. :
Code
void rmnimbus_state::fdc_reg_w(offs_t offset, uint8_t data)
{
	if((offset == 0) && ((data & 0xF0) == 0xD0))
		wait(64);

	m_fdc->write(offset,data);
}

Cheers.

Phill.

PhillHS #119934 10/28/21 09:06 PM
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Create an emu_timer device and ->adjust() it to go off in whatever time you need.

PhillHS #119935 10/29/21 07:04 AM
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You do whatever you want for you locally, of course, but I'm 98.5% certain there is no hardware in the nimbus to detect when a Dx value is written to the command register address and insert a bus delay in that case. So that wouldn't be accepted as-is, unless you have a way to prove there is such a thing.

As for the interrupt, the bios uses d0. That's a "gentle" interrupt we're probably running as too harsh, it's d8 that forces immediate stop. So I think we need to let the current action complete if it's a read or a write (not a search), which would probably do nicely with the rmnimbus.

The timing changes, otoh, why do you need them, what is happening in the bios?

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PhillHS Offline OP
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Originally Posted by Olivier Galibert
You do whatever you want for you locally, of course, but I'm 98.5% certain there is no hardware in the nimbus to detect when a Dx value is written to the command register address and insert a bus delay in that case. So that wouldn't be accepted as-is, unless you have a way to prove there is such a thing.

Because my suggestions for altering the timing of the floppy code where 'rejected' and without them the machine's emulation doesn't work.

The Nimbus does inser 2 wait states in any transaction on the expansion bus (where the disk card is attached), However this only seems to have a significant effect on the force interrupt.

Quote
As for the interrupt, the bios uses d0. That's a "gentle" interrupt we're probably running as too harsh, it's d8 that forces immediate stop. So I think we need to let the current action complete if it's a read or a write (not a search), which would probably do nicely with the rmnimbus.
I had implemented the write changes in the wd_fdc code, which seemed to work for writes as suggested in the other thread. I did try with reads but couldn't get it to work.


Quote
The timing changes, otoh, why do you need them, what is happening in the bios?
[/quote]
Not the bios but in the 'chipset' which as said above inserts wait states.

Cheers.

Phill.

PhillHS #119937 10/29/21 01:52 PM
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The correct way to insert wait states is m_cpu->adjust_icount(-number_of_cycles). So if it's a 4 cycle wait, you'd adjust by -4.

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PhillHS Offline OP
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Originally Posted by R. Belmont
The correct way to insert wait states is m_cpu->adjust_icount(-number_of_cycles). So if it's a 4 cycle wait, you'd adjust by -4.

Ahhh I did wonder about that, and looked through the code to see if there was an obvious way of doing that but didn't find it. I'll try that then.

Cheers.

Phill.


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