is someone still interested in researching AICA filter EG ?
have some progress with this:
at first I've taken this filter formula http://www.musicdsp.org/showone.php?id=185
, because using Neil's I can't get any resonance.
as for coefficients: I think FEG values (both filtering coeff and Q) uses the same dB logarithmic volumes as AEG but with 3 more LSB added. So in short - Neill was one bit wrong, it have 9 fractional bits and 4 exponential (not 8 and 5).
In the case of Q it must be <<=6 so it become in same dB range as FEG level.
this assumptions also kind of approved by old AICA implementation http://sabia.tic.udc.es/gc/Contenidos%20...CA_E.HTM#no6_17
, when at some stage of development Q register was full 13 bits, not just 5bits as in final version.
so currently I have this (messy) code:
#define F_FRAC_BITS 6
#define F_ALL_BITS 10
// FEG_Level (13 bits -> 10 bits)
u32 c_db = (chan->feglevel) >> (13 - F_ALL_BITS);
// FEG_Level - (Q - 3dB), add/sub of dB values equal to mult/div of linear R and C coefficients
s32 rc_db = (chan->feglevel - ((chan->q << 6) - 0x100)) >> (13 - F_ALL_BITS);
LIMIT(rc_db, 0, ((1 << F_ALL_BITS) - 1));
s32 c_lin = (((c_db & ((1 << F_FRAC_BITS) - 1)) | (1 << F_FRAC_BITS)) << (F_ALL_BITS - F_FRAC_BITS - 1)) >> ((c_db >> F_FRAC_BITS) ^ ((1 << (F_ALL_BITS - F_FRAC_BITS)) - 1));
s32 rc_lin = (((rc_db & ((1 << F_FRAC_BITS) - 1)) | (1 << F_FRAC_BITS)) << (F_ALL_BITS - F_FRAC_BITS - 1)) >> ((rc_db >> F_FRAC_BITS) ^ ((1 << (F_ALL_BITS - F_FRAC_BITS)) - 1));
s32 inv_rc_lin = (1 << F_ALL_BITS) - rc_lin;
chan->feg_v0 = inv_rc_lin * chan->feg_v0 + c_lin * s - c_lin * chan->feg_v1;
chan->feg_v0 >>= F_ALL_BITS;
chan->feg_v1 = inv_rc_lin * chan->feg_v1 + c_lin * chan->feg_v0;
chan->feg_v1 >>= F_ALL_BITS;
s = chan->feg_v1;
which gives IMO nice result "close enough" to real thing
here few recordings for comparison:
real DC http://rghost.ru/8ctcKWMtb
Sega GT sound test track 01
real HW https://www.youtube.com/watch?v=oH6gW2bxaJk
But... there is some problem in algorithm. by design it makes sound a bit off/quiet (then C 1 and Q 0 output becomes = input minus previous output), so with Feg_Lv 0x1FF8 and Q 4 output is not the same as input.
is there anyone good at DSP processing and may give advice to look at some another filtering algorithms/formulas ?