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About Seiken Densetsu 3, there's certainly a bug regarding that garbage at the top of the talk bar, surely there's a couple of bug in the current mode 5/6 implementation I wasn't just talking about the garbage. Any time there's even a single visible scanline of hires anywhere on the screen you need to render the entire frame at 512 resolution, otherwise you're throwing ("half-")pixels away. Then again...there's a bug in the mode 5/6 implementation that makes some pixels to be "thrown away"... check the charset 6 on snap 1 and charset 3 on snap 2. ![[Linked Image from mamedev.emulab.it]](http://mamedev.emulab.it/kale/fast/files/0199.png) ![[Linked Image from mamedev.emulab.it]](http://mamedev.emulab.it/kale/fast/files/0200.png) Could also be that calling a single line of mode 5 makes the entire screen to be 512x224, but again we are into the same theory league as who shot JFK... And in the end...I'm referring as "internal framebuffer" the thing that converts the digital format to something usable by an analog device like a TV, the DAC in short.
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Joined: May 2009
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And in the end...I'm referring as "internal framebuffer" the thing that converts the digital format to something usable by an analog device like a TV, the DAC in short. But that's not the way a RAMDAC works.
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Joined: Aug 2009
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Go Go Ackman 2 hangs are caused by main<->sound cpu comms rather than timing, setting the interleave to perfect fixes the hangs on it.
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Joined: Mar 2001
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Yeah, I just fixed kinstb in MAME by doing that (not that you can tell because the list is still broken). And perfect interleave makes Actraiser fart several times before it hangs ;-)
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The correct fix is to have a separate S-CPU core that's clocked at SNES master (21.whatever) and have everything take the right amount of cycles from there. Anything else will just cause trouble later. Ok, I'm going to see this one, the plan is: * Add a new CPU core, 5A22, that is a clone of G65816 with just a different CPU_EXECUTE (that contains a cycles*6 instead of cycles in this function) * Modify SNES and friends driver to have this new core with clock = master clock instead of clock / 6 * Start to hook up all the cpu eat cycles where needed... Is it a good plan?  EDIT: part one of the plan doesn't already work as expected... 
Last edited by Kale; 08/17/09 04:29 PM.
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Joined: Mar 2001
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The plan I was going for was to clock it at 21.whatever and have each cycle of each instruction eat the appropriate number of master clocks depending on the speed switch, fast/slow ROM, etc. That way you don't need eat_cycles instructions all over the place.
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Joined: Aug 2009
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You mean doing all of this inside the cpu core and having extra internal states like the slow/fast ROM, right?
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Joined: Mar 2001
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Right. The H8 core does something similar-ish where there's an internal function that given an address computes the number of clocks needed to access it and all the opcodes are built on that.
Technically all the 4xxx registers should be internal to the core also but I could see that causing trouble for HDMA etc.
Last edited by R. Belmont; 08/17/09 04:55 PM.
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Feel free to use this as PD. Many people have tried to improve it (with lookup tables, ternary, only one return point, etc), but none have succeeded  unsigned sCPU::speed(unsigned addr) const {
if(addr & 0x408000) {
if(addr & 0x800000) return fastROM;
return 8;
}
if((addr + 0x6000) & 0x4000) return 8;
if((addr - 0x4000) & 0x7e00) return 6;
return 12;
}Set (unsigned)fastROM to 8 on reset, and on $420d.d0 writes, set to (d0 ? 6 : 8); If you stick this function inside the bus_read() and bus_write() functions, the core of your CPU won't ever need to manually specify eat_cycles() calls.
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Joined: Mar 2001
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Nice  Thanks byuu!
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