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Woot indeed. Good job guys!

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MESS SVN #7566 passes all 4 ADC/SBC test programs. Woot!

Great laugh

And as for:
http://www.allgoodthings.us/mambo/i...42&func=view&catid=2&id=3791

My turn to say this back at Cowering ... "hopefully some of the other emu authors will fix their code" :P

[Linked Image from byuu.org]
(and my screenshot isn't double-width xD)

But I'll be nicer wink

http://byuu.org/temp/test_math.zip
http://bsnes.googlecode.com/files/bsnes_v062.zip

There is one small caveat. It seems real hardware will freak out on rare occasion if you strobe the registers too quickly. You'll see in my test_math.ufo file that there are three invalid bytes. They are essentially being ORed with ... something.

When this ORing happens depends on the individual SNES (different even for the same CPU/PPU1/PPU2 combination), and it is consistent (eg repeatable); and blargg has one that doesn't OR results at all.

The important point though is that the underlying algorithms are correct, as is the timing.

byuu #60131 03/14/10 10:34 AM
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Originally Posted by byuu
Quote
MESS SVN #7566 passes all 4 ADC/SBC test programs. Woot!

Great laugh

And as for:
http://www.allgoodthings.us/mambo/i...42&func=view&catid=2&id=3791

My turn to say this back at Cowering ... "hopefully some of the other emu authors will fix their code" :P

[Linked Image from byuu.org]
(and my screenshot isn't double-width xD)

But I'll be nicer wink

http://byuu.org/temp/test_math.zip
http://bsnes.googlecode.com/files/bsnes_v062.zip

There is one small caveat. It seems real hardware will freak out on rare occasion if you strobe the registers too quickly. You'll see in my test_math.ufo file that there are three invalid bytes. They are essentially being ORed with ... something.

When this ORing happens depends on the individual SNES (different even for the same CPU/PPU1/PPU2 combination), and it is consistent (eg repeatable); and blargg has one that doesn't OR results at all.

The important point though is that the underlying algorithms are correct, as is the timing.

Fantastic, this is the kind of guy we need running tests on the Seibu COP stuff, Dox doesn't have the patience to figure out what the seemingly random / unexpected results he gets are, and why we're getting them and how to avoid them ;-) (I concede, it doesn't make much sense tho) Some random addition / xoring going on there too, even on the 'simple' memcpy routines ;-/

Haze #60132 03/14/10 12:00 PM
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The funny thing about Cowering posting that is the code for it was promptly ripped back out for breaking everything else smile

Also, MVN/MVP are perfectly useful on systems that actually have more than 128k of RAM, although it'd be nice if the extra 3 cycles/byte had been fixed. That's the cost of the world's last hand-laid-out processor I guess.

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The funny thing about Cowering posting that is the code for it was promptly ripped back out for breaking everything else

Yeah, it didn't bother me at all, it was just kinda funny. The presumption that I wasn't aware of something so basic after all the stuff I've uncovered smile

Either way, I'm glad he brought it up and gave me the motivation to look at it again. It's wonderful to have one more nightmare behind us.

The final things left to do:
* S-CPU auto joypad poll timing
* S-CPUr1 HDMA crash detection
* S-CPU<>S-SMP port ORing
* S-SMP timer glitching
* S-SMP TEST register
* S-DSP mute pulse
* pseudo-random initialization of memory
* full cycle-level emulation of the S-PPU

If we get all of that, I will consider emulation as close as the difference between hardware revisions.

Quote
Also, MVN/MVP are perfectly useful on systems that actually have more than 128k of RAM, although it'd be nice if the extra 3 cycles/byte had been fixed. That's the cost of the world's last hand-laid-out processor I guess.

It has such an immense cost per byte. 56 cycles/byte, whereas DMA is 8 cycles/byte.

byuu #60142 03/14/10 07:43 PM
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Sure. But back in the real world that's 7 cycles/byte, DMA doesn't exist, and you have a 320x200 framebuffer with per-scanline palettes, H-INTs and optional RLE mode. No separate sound CPU, but you've got a chip that can play 32 channels of 8-bit samples by DMA. Now show solid-filled rotating polygonal objects with scrollers and music and starfields (and yes, people did).

The CPU wasn't designed for Nintendo, it was designed for Apple and Commodore. Once you understand that, it makes more sense smile

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What about the timing sync stuff between S-CPU and S-SMP/APU? I thought someone tried to test that and blew up their copier or something bad like that? I'm not even sure how that's possible...

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Heh, blargg and I just spent eight hours researching the S-SMP TEST register. You guys are going to give up and quit when you see just how complex it really is, heh. It is, without a doubt, the craziest 8-bit register I've ever seen in my life. And we're still going.

http://byuusan.kuro-hitsuji.net/blargg_2010-03-14.zip

Quote
What about the timing sync stuff between S-CPU and S-SMP/APU? I thought someone tried to test that and blew up their copier or something bad like that? I'm not even sure how that's possible...

My UFO 8.3j's RAM stopped working after trying it. Probably a bus conflict damaged it. It came back to life after 1.5 years of disuse, too. It may have been a coincidence, but at $200 a pop, I wasn't going to try again.

blargg tried it on hardware, it ORs between the old value and new value, but only on some bits, and only some of the time. Need pseudo-randomness and an extreme timing system to simulate it. Bit-perfect emulation of it is a misnomer.

byuu #60173 03/15/10 04:31 PM
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Super Kick Boxing has some graphic glitches again... frown

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might be the same problem as r-type 3. if so, I'm trying to fix it... let's see how it does work out (especially because I have improvements to sprites waiting to be added smile )

of course, I would appreciate a lot if you can help to narrow down when the regression happened wink

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