I'm told that DSP-2/3/4 are coming
As soon as we can raise $750 in donations
I'm going to pitch in $150 myself this time, and Lord Nightmare is going to donate the cartridges, so we need $600 more. If you're interested in helping:http://board.byuu.org/viewtopic.php?f=16&t=1249
My emulation is now good enough to get in-game on Super Mario Kart, but I'm completely stumped at this point. Still, if we can get past these hurdles, we can literally plug in and play the DSP-2,3,4 games.
Multiplication happens after each opcode, K*L is put into M,N. But it mentions the result is 30-bit with a sign bit. Isn't that the same thing as 31-bit? Or is it possible it is acting like the sign bit of the flag registers, and just mirroring the highest bit?
What is the order of operations for OP/RT? Take this example:
4eb inc a
To dump the data ROM correctly, we have to do the mov first, and the inc second.
The way I've implemented it was to do the inc read, then the mov read, then the inc write, then the mov write.
Both have the ability to manipulate both the IDB register and any shared registers.
It is at least somewhat clear from the documentation that the DPL, DPHM and RP adjustments happen at the end of the opcode.
How in the hell do we calculate the OV1 flags? The documentation says it's set to 1 if there were an odd number of the three overflows. What three overflows?
What about the S1 flag? Is it set to 1 on a positive overflow, or set to 1 on a negative overflow? What happens if there is no overflow, does it get set to zero always then?
The SGN register may be a useful hint to figuring this one out.
Am I even calculating OV0 correctly?
CMP (one's complement) is just !Q, right? They would say NOT if they wanted ~Q.
How exactly does XCHG work? The document says it's an 8-bit exchange. Which 8-bits, the top eight or the bottom eight? It updates the S0 flag which is suspicious for the bottom eight.
What is up with KLM mode? The nicer doc says you read from RAM[DP | 0x40], while the uglier one says that you read from RAM[(DP & 0x3f) | 0x40]. They list it as HiRAM, yet it forces D6=1 rather than D7=1. And just out of curiosity, why the fuck does it force D6=1? What possible use is that?
The stack has four levels, and it is LIFO. So what happens when you pull an address off the stack? Does the now empty slot at the end get set to zero, or keep the previous address, or does it act more like a ring buffer and move the old first value to the last value?
When SR.DRC=0 (eg 16-bit DR transfer mode), does RQM get cleared for each 8-bit write, or only after two 8-bit writes (eg after a full 16-bit transfer)?
What happens to the high 8-bits of the 16-bit DR register when you write to it from the S-CPU in 8-bit DR transfer mode? Does it keep whatever was there, or is it forced to zero ala 65816 index registers?