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Joined: May 2009
Posts: 2,024 Likes: 60
Very Senior Member
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Very Senior Member
Joined: May 2009
Posts: 2,024 Likes: 60 |
Welp, I've got everything hooked up, I just need to, erm, dump the ROMs off of my legally-owned cartridge and I'll be good to go.
EDIT: I'll bite, how the fuck do I regenerate the driver list in our godawful new build system?
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Joined: May 2009
Posts: 2,024 Likes: 60
Very Senior Member
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Very Senior Member
Joined: May 2009
Posts: 2,024 Likes: 60 |
Hangs on "TRANSMIT WAIT":
Soft reset
Unknown ST0018 write from ARM: 4000002c = 00000002 (& ffffffff)
Unknown ST0018 write from ARM: 40000020 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000024 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000028 = 00000000 (& ffffffff)
ST0018: ARM state read
ST0018: ARM state read
Unknown ST0018 write from ARM: 40000020 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000024 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000028 = 00000000 (& ffffffff)
ST0018: ARM state read
Unknown ST0018 write from ARM: 40000020 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000024 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000028 = 00000000 (& ffffffff)
ST0018: ARM state read
...(repeats lots of times)...
ST0018: CPU status read
ST0018: CPU status read
ST0018: ARM state read
Unknown ST0018 write from ARM: 40000020 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000024 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000028 = 00000000 (& ffffffff)
ST0018: CPU status read
ST0018: CPU status read
ST0018: ARM state read
Unknown ST0018 write from ARM: 40000020 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000024 = 00000000 (& ffffffff)
ST0018: CPU status read
Unknown ST0018 write from ARM: 40000028 = 00000000 (& ffffffff)
ST0018: CPU status read
ST0018: ARM state read
ST0018: CPU status read
Unknown ST0018 write from ARM: 40000020 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000024 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000028 = 00000000 (& ffffffff)
ST0018: CPU status read
ST0018: ARM state read
ST0018: CPU status read
Unknown ST0018 write from ARM: 40000020 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000024 = 00000000 (& ffffffff)
Unknown ST0018 write from ARM: 40000028 = 00000000 (& ffffffff)
CPU never seems to write anything to the ARM, just read it. What do?
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Joined: Jun 2008
Posts: 205
Senior Member
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OP
Senior Member
Joined: Jun 2008
Posts: 205 |
At reset, you should see the CPU writing #$00, #$01, #$00 to $3804 to reset the ARM CPU. You can basically ignore that for all it's worth for now. $3804 needs to return d7 set. You should then see it write #$f1 to $3802. If it's not doing that, then we are hitting a CPU emulation bug in MESS. In which case ... how insane would it be to hook the MESS ARM core into bsnes? As I assume the bsnes CPU core into MESS would be even harder  Apologies but I'm about to sleep for tonight, have to get up in a few hours for work, and I'll be on then.
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Joined: May 2009
Posts: 2,024 Likes: 60
Very Senior Member
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Very Senior Member
Joined: May 2009
Posts: 2,024 Likes: 60 |
At reset, you should see the CPU writing #$00, #$01, #$00 to $3804 to reset the ARM CPU. I don't - at least I don't think, and I can't check since I'm posting from bed, but I sincerely doubt an ARM issue would prevent the 65816 from *ever* issuing a write to the ARM. I'll take a look tomorrow evening.
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Joined: Jun 2008
Posts: 205
Senior Member
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OP
Senior Member
Joined: Jun 2008
Posts: 205 |
As long as you have $3804 returning d7 set, you are correct. There doesn't even need to be an ARM CPU core there; the CPU will write #$f1 to $3802, which should set status bit d3 until the ARM reads it from 40000010.
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Joined: May 2009
Posts: 2,024 Likes: 60
Very Senior Member
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Very Senior Member
Joined: May 2009
Posts: 2,024 Likes: 60 |
As long as you have $3804 returning d7 set, you are correct. There doesn't even need to be an ARM CPU core there; the CPU will write #$f1 to $3802, which should set status bit d3 until the ARM reads it from 40000010. Why would $3804 return D7 set? I seem to recall D7 is bridge.ready or something. I don't recall seeing anywhere that you initialize bridge.ready, so I initialized it to false in my code. Are you somehow inadvertantly relying on an uninitted bool defaulting to true?
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Joined: Mar 2001
Posts: 16,892 Likes: 51
Very Senior Member
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Very Senior Member
Joined: Mar 2001
Posts: 16,892 Likes: 51 |
It's more likely a mapping issue if writes aren't making it to the ST-0018.
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Joined: May 2009
Posts: 2,024 Likes: 60
Very Senior Member
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Very Senior Member
Joined: May 2009
Posts: 2,024 Likes: 60 |
It's more likely a mapping issue if writes aren't making it to the ST-0018. I shouldn't have one because I'm redirecting all writes between address $3800 and $38FF inside the write handlers for the $00-$2F bank, the $30-$3F bank, and the $80-$BF bank.
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Joined: Jun 2008
Posts: 205
Senior Member
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OP
Senior Member
Joined: Jun 2008
Posts: 205 |
Well, fuck: http://board.byuu.org/viewtopic.php?p=57219#p57219> Why would $3804 return D7 set? d7 is the "ARM ready" flag. It is set in registers.hpp:Bridge::unsigned operator(). The flag is actually set to true inside ARM::enter(), after the reset phase completes. If you set $3804.d0 to 1, it disables the ARM CPU. When you set it back to 0, the chip resets itself and then after it's done, will set the d7 flag to ready again. The chip is enabled at power-on, it does not need to be turned on manually.
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Joined: May 2009
Posts: 2,024 Likes: 60
Very Senior Member
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Very Senior Member
Joined: May 2009
Posts: 2,024 Likes: 60 |
That explains it. Thanks for the info! 
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