Guys, I am only trying to find out why the current implementation (even with newest floppy code ***) is so unreliable Isn't it possible that the 'shared memory' arbitration we talked about synchronizes both CPUs - and we miss important details?
When i look at the signals passed at the J1 connector (left = computer; right = floppy
) i can't find evidence that the Z80 is halted by the RX50 controller -https://dl.dropboxusercontent.com/u/37819653/RX50_Controller_5415482.png
@R.Belmont: there is a 500 ms delay between MOTOR ON and DISK SELECT (middle part). How is that implemented best?The following bugs remain in current SVN:a.
occasional deadlocks between Z80 and 8088 (near or at HLT instruction).
-> CPU communication / timing? Z80 core?b.
DOS 2.x and CPM 2.x booters fail (CP/M BDOS: 'Read error at track 2 sector 1').
-> The bootstrapper (1) loaded via READ SECTOR, the 2nd part begins with READ ID and fails
-> Think it is command 0xc0; see also my post here
CP/M 1 -sometimes- prints segment addresses to the console
-> crashes during floppy operation...?d.
UCSD systems probe A,B,C then D - and lock up if not all 4 drives have images attached.
-> Drive detection!
(***) preliminary version (patch against 30456):https://dl.dropboxusercontent.com/u/37819653/_Prelminiary_PATCH_for_SVN_30456.diffhttps://dl.dropboxusercontent.com/u/37819653/_MISSING_FILES_for_SVN_30456.7z