I verified the SR16 ROM dump. I also confirmed that the ROM word address decoder is the same as other TMS-1000s. The instruction TDO is modified from a standard TMS-1000 to also decrement Y, but that's the only difference I've found.
Gotcha- I left the die so the text is upright (with the RAM in lower left), then read the bits TtoB, LtoR. That is the same as rotating the die CCW 90 degrees and reading the bits LtoR, BtoT.
4-5 of the bits are really still unreadable, but they are in the digits 9-8-7, so there's not really any question. And the ones in the AND section can be deduced if you can see the adjacent bits. Next time I use some acid on a chip I'll give this one another minute to be sure.
I was thinking some more about the 0980 word order. I used the ROM word address decoder to reorder the bits, and that made it match the patent word order, so that makes me think that it is correct. The object code in the Star Wars patent specifically stated "Program Counter Sequence" - I wish this one did, too.
I guess another possibility is that reset starts execution somewhere else. The other games start out by initializing RAM, so these should, too.
Do your changes allow disassembling the 0980 code so we can see if it makes any sense?
I just found in US4064554 that the 0980 program counter and ROM page address register are both set to 0 by power-up clear circuitry.
Now I've confused myself about "program counter sequence". I interpreted that to mean execution order, but the bytes in the Star Wars patent 4270755 are in the same order as I read them off the die, which is not execution order. The 6-bit LSFR sequence has to be used to execute them.
For the 0980, are you using the 7-bit LSFR sequence that the circuit in Fig 19 generates?
Here you go. It's very similar to TMS1000 of course, except no chapter bit, PC goes to 127, and there are 9 bits instead of 8.
FOR page=0 TO 15 && 16 pages in each row
FOR pc=0 TO 127 && 128 rows = program counter
FOR bit=8 TO 0 STEP -1 && 9 bit ROM