Home Page Forums MAME MAME TMS-09xx/1xxx thread (was New Dumps)

I verified the SR16 ROM dump. I also confirmed that the ROM word address decoder is the same as other TMS-1000s. The instruction TDO is modified from a standard TMS-1000 to also decrement Y, but that's the only difference I've found.

I got a better view of the TI Programmer output PLA. Not great, but what I transcribed makes sense. Here are the bits from top to bottom, left to right:

00100000 01101001
00000000 10101001
01100101 01010110
11011110 01010101
10000000 10010110
10001000 10010101
10100000 01100110
00000110 01100101
01100010 10100110
10001001 10100101
00100100 01011010
10000010 01011001
00001100 10011010
01000000 10011001
01100111 01101010
00000001 10101010

This maps to
9 9
8 8
7 7
F r
6 6
E E
5 5
D d
4 4
C C
3 3
B b
2 2
A A
1 1
0 0

It's interesting that they used 0xF for "r" instead of "F", since "r" is only used to display "Error".

Got it, thanks!

You reordered them upside-down, I suppose?
FWIW this is my temp. one. I rotate the die pic so RAM is at bottom-right and literally type the bits manually.

Gotcha- I left the die so the text is upright (with the RAM in lower left), then read the bits TtoB, LtoR. That is the same as rotating the die CCW 90 degrees and reading the bits LtoR, BtoT.

4-5 of the bits are really still unreadable, but they are in the digits 9-8-7, so there's not really any question. And the ones in the AND section can be deduced if you can see the adjacent bits. Next time I use some acid on a chip I'll give this one another minute to be sure.

I was thinking some more about the 0980 word order. I used the ROM word address decoder to reorder the bits, and that made it match the patent word order, so that makes me think that it is correct. The object code in the Star Wars patent specifically stated "Program Counter Sequence" - I wish this one did, too.

I guess another possibility is that reset starts execution somewhere else. The other games start out by initializing RAM, so these should, too.

Do your changes allow disassembling the 0980 code so we can see if it makes any sense?

Nope, the disassembler/debugger is still not very good. Though I can see there are no 'illegal' instructions in your raw_to_980 conversion, so that part should be good.

Could you post your algorithm of it? Maybe I can try out a few combinations.

*edit* ok, i tried the 16 possible reset vectors for the current 0980 dumps(set pa/pb at reset, default value: $0F), none of them init RAM

I just found in US4064554 that the 0980 program counter and ROM page address register are both set to 0 by power-up clear circuitry.

Now I've confused myself about "program counter sequence". I interpreted that to mean execution order, but the bytes in the Star Wars patent 4270755 are in the same order as I read them off the die, which is not execution order. The 6-bit LSFR sequence has to be used to execute them.

For the 0980, are you using the 7-bit LSFR sequence that the circuit in Fig 19 generates?

0 1 3 7 15 31 63 127 126 125 123 119 111 95 62 124
121 115 103 79 30 61 122 117 107 87 46 92 56 112 97 67
6 13 27 55 110 93 58 116 105 83 38 76 24 49 98 69
10 21 43 86 44 88 48 96 65 2 5 11 23 47 94 60
120 113 99 71 14 29 59 118 109 91 54 108 89 50 100 73
18 37 74 20 41 82 36 72 16 33 66 4 9 19 39 78
28 57 114 101 75 22 45 90 52 104 81 34 68 8 17 35
70 12 25 51 102 77 26 53 106 85 42 84 40 80 32 64

doublechecked, yes I am.
Underneath, the LFSR is exactly the same as TMS1000, just 1 bit more.

Grasping at straws, have you tried executing the bytes sequentially, not using the LFSR sequence? The 0980 ROM array rows are in a different order from the TMS1000/1100/0970, so maybe???

yup, i've tried that too.
Could you post your algo for converting 0980 raw to good?

Here you go. It's very similar to TMS1000 of course, except no chapter bit, PC goes to 127, and there are 9 bits instead of 8.