Regarding the emulation of bus timing as mentioned in the shout box recently, where intelligent carts with fast microcontrollers etc insert data into running systems, I have the opposite need when emulating the 68K DTACK.
In a single CPU system it can mainly be ignored but in a VME system there is an arbiter than can postpone a request over the bus infintelly by not granting the bus request until the bus is clear, so then the asynchrounous nature of the 68K upto 68030 is more important.
Any suggestions how this can be handled in MAME?
Will it just work if the read/write handler hangs on the arbiter until the bus request finishes? What about eating clock cycles?