Is it possible to have separate handlers for 8, 16, 32 and 64 bit accesses in the *same* address space. It seems that the memory system will use the first-fit rather than the best-fit, is this correct?
I'd like to trigger VME bus in 4 different addresspaces (A16, A24, A32 and A64) with four different data widths (D8, D16, D32 and D64).
Even an 8 bit CPU can actually trigger any of these through the VME bus device, but usually a 68K like CPU.
Last edited by Edstrom; 11/23/15 01:00 PM.