Exactly, the latter has blown up in my face, at least a bit.
So, if I define just one handler for the max width to handle all access types, say a handler for D16 word access at a specific memory range and the CPU accesses it by byte I find that the handler still get a word access.
I want to find out the 'mask' used for that word access to know if it is the even or odd byte that is accessed. Also for D32 of course.
I don't want to map the slot devices in the maincpu address space but in the VME bus adress spaces since the local addresses can differ from the global bus addresses. This makes it difficult for the VME device read/write handler since there is no information about the width. See page 2-12 in the VME bus specification
It is quite common to strap identical slave slot devices to map to different VME adresses OR, a little less common, to different bits on the same VME adress. The latter allows for reading multiple I/O boards in the same VME bus cycle. So even if I leave this special use cases for the future I'd like to prepare the design for it, if possible.