Well in VME the A1-A23 is called A24 adressing and there is no A0. The 68000 just happens to be the role model for the VME bus but there are plenty of other CPU architectures using it and still have to implement A24! smile There are other lanes used to pick up what byte that is transfered for example for byte transfers in A32 mode.

Another interesting detail about VME A24 mode is that it is the maximum addressable memory area that only requires the P1 connector. For either A32 and/or D32 transfers the second connector P2 is required and there is a bunch of rules how boards can be combined with only P1 or both connectors.

Maybe there is a simple workaround for A24? I am trying to set up one address space per addressing mode A16, A24, A32 and A64. In theory there are 256 different Address Modifiers (AM) which could be mapped to one address space each but I will ignore that now and assume people set up systems based on one or more of the above 4 systems. The AM:s will only be emulated to verify that both the master and slave device agrees on the transfer type.

I think I start with A16 with D8 and D16 transfers until you in the core team decides on the A24 thing.

I would also appreciate advice on how to define the four address spaces, I was thinking just to use AS_0 to AS_3 in the VME device I am creating and map accesses through the read and write handlers from the local AS_PROGRAM address space(s) of the board(s)? Will they not collide internally as the VME device itself is owned by the CPU board in SLOT 0?

The plan is to let the VME device be a slot device and access the other boards through plain slot mapping to one of the four address spaces described above. Some sub-master boards has dual ported RAM as interface to the VME bus and subsequently their own address maps.

Last edited by Edstrom; 11/24/15 10:41 PM.

Because I can