Originally Posted By Edstrom
JThe direction I have is to model the VME adress spaces (A16, A24, A32 and A64) independently of the address space of the CPU board and map slot devices into those.

That sounds like a bad idea actually.

Can you describe what happens when the cpu does an access? What makes the bus decide it's for him, what actually goes on the bus, what the devices see, what they do?