On another note: the CPU-ID program on RBDS31UT.IMD claims we "incorrectly allow interrupts after a change to SS" (see screenshot).
Old 8088 CPUs (before 1981) had this bug. Is that behaviour wanted / correct?
Assembler source from CPU ID 1.42
Hunt for FLG_CERR to find the code to exhibit the bug.
on line 1406 in i86.cpp should make that work properly as according to this
it works for every segment register on every 16-bit x86 cpu (except the 286 which already handles it properly).