Well, remember, the bus on the tms6100 (like the ctrl bus on the tms5100) is bidirectional but needs one cycle to switch states. I assume a load address command switches it to input, an idle command does nothing (prev state remains), a read bit command switches it to output, and read and branch may do nothing and leave the state alone, not clear. The PLA in the speak and spell patent (US4189779 pdf pages 42-52, i.e. figures 19, 20 and 21, see http://www.pat2pdf.org/patents/pat4189779.pdf or https://www.google.com/patents/US4189779 ) explains when the state switches, I think?


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