Here's a Logic capture of me dumping the first 6 bytes from CD2601. It starts off with a dummy address load and dummy read, then I load an address of 00000 (I tried both 4 and 5 nibbles, and got the same results), then another dummy read. Then I clock M0 and read the bytes, LSN first: 8 C 3 0 E C 3 0 3 D 3 0 = C8 03 CE 03 D3 03, which are pointers to the first 3 words at addresses 3C8 (ABSENT), 3CE (ALERT), and 3D3 (ALIKE).

This is with pins 1-4 as DATA/ADDR 1,2,4,8, pin 5 as CLK, pin 8 as M0, pin 10 as M1, pin 11 CS tied to VSS, pins 6, 7, and 13-16 NC.

Note that CLK is just held high, and the PIC that I used to toggle M0 and M1 also created the "flag" signal that indicates when data is valid (based on waiting a few clocks after the falling edge of M0).

You can see that the new byte is not yet valid on the rising edge of M0, although the old byte is still valid. Neither the old nor new byte is valid immediately after the falling edge of M0. This seems compatible with the timing diagram in the data sheet.

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