Yeah- here are captures with M0 held hi 2 clocks, 3 clocks and 4 clocks. I'm measuring up to 13.8 uS from M0 rising edge until last data bit settles. So I guess that is different from the data sheet, which shows the data bits transitioning while M0 is low.
I have some 28SDIP TMS6100 VSMs that I could dump and compare captures with, if that would be useful. CD2307A, CD2354A, CD2394A, CD2395A.