I wonder if something about the O PLA is different on this chip. When you release a TMS1100 from reset, that clears the O register, so the PLA entry for 0 is output. After making changes to the timing of the dumping process, I noticed glitches in O7 that corresponded to ROM bits that had bit 7 low. But the glitches weren't in identical places on multiple dumps. Then I put a pulldown resistor on O7, and that made all the dumps match. So it looks like O7 is not being driven for a brief moment after reset is released if the bit is low. But the other rev E chips that I tried didn't respond like that.
