Well, DEC manuals state the FDC code has a 'sweet spot' (whatever that tells us). I may have to look that paragraph up.
(i dont want to argue...)
Found a description of the wait state logic, as described by DEC:
![[Linked Image from dl.dropboxusercontent.com]](https://dl.dropboxusercontent.com/u/37819653/BANNISTER/RX50_controller_needs_more_time-see_TM_p.115.png)
(Technical manual, PDF page 115)
WAIT logic (DUELL schmatics, saved from Shoutbox):
![[Linked Image from dl.dropboxusercontent.com]](https://dl.dropboxusercontent.com/u/37819653/BANNISTER/WAIT_Z80_Duell_Schematics.jpg)
Sorry for the bad quality.