Is the 68030 cycle accurate enough for register to register calculations and DIV arithmetics? The Force CPU-30 firmware code below uses the timer to meassure the time it takes to execute some code to determine what CPU is on the board. Should it work? If so I need to fix the timer I just implemented.

Code:
FFE033C6: movem.l D1-D6/A5, -(A7)
FFE033CA: movec CACR, D2; (2+)
FFE033CE: move.l  D2, -(A7)
FFE033D0: moveq   #$0, D1
FFE033D2: movec D1, CACR; (2+) // Disable cache
FFE033D6: move    SR, D3
FFE033D8: move.l  D3, -(A7)
FFE033DA: move    #$2700, SR   // Disable all interrupts
FFE033DE: lea     $ff800e00.l, A5 // 68230 PIT base
FFE033E4: move.b  #$0, ($10,A5)  // TCR - timer disabled 
FFE033EA: move.b  #$ff, ($13,A5) // Preload Hi
FFE033F0: move.b  #$ff, ($14,A5) // Preload Mid
FFE033F6: move.b  #$ff, ($15,A5) // Preload Lo
FFE033FC: move.l  #$4e20, D0
FFE03402: move.l  #$3, D1
FFE03408: move.l  #$2, D2
FFE0340E: move.l  #$2, D3
FFE03414: move.b  #$1, ($10,A5) // Timer enabled
FFE0341A: move.l  D2, D4
FFE0341C: move.l  D3, D5
FFE0341E: move.l  D1, D6
FFE03420: divs.l  D6, D2:D3; (2+)
FFE03424: subq.l  #1, D0
FFE03426: bne     $ffe0341a // loop for $4e20 times
FFE0341A: move.l  D2, D4
FFE0341C: move.l  D3, D5
FFE0341E: move.l  D1, D6
FFE03420: divs.l  D6, D2:D3; (2+)
FFE03424: subq.l  #1, D0
FFE03426: bne     $ffe0341a // loop for $ffffffff times

   (loops for 119988 instructions)

FFE03428: move.b  #$0, ($10,A5) // disable timer
FFE0342E: moveq   #$0, D0
FFE03430: move.b  ($17,A5), D0 // counter register Hi
FFE03434: lsl.l   #8, D0
FFE03436: move.b  ($18,A5), D0 // counter register Mid
FFE0343A: lsl.l   #8, D0
FFE0343C: move.b  ($19,A5), D0 // counter register Low
FFE03440: not.l   D0
FFE03442: lsr.l   #4, D0
FFE03444: lea     ($22,PC), A5; ($ffe03468)
FFE03448: move.w  (A5)+, D1
FFE0344A: cmp.w   D1, D0     // Apparantly looking up timer result in table
FFE0344C: bhi     $ffe03454
FFE03450: addq.l  #2, A5
FFE03452: bra     $ffe03448
FFE03448: move.w  (A5)+, D1
FFE0344A: cmp.w   D1, D0
FFE0344C: bhi     $ffe03454
FFE03450: addq.l  #2, A5
FFE03452: bra     $ffe03448

EDIT: Apparantly this is only for the clock detection of the board and I am currently off by a factor two approximately but still outside the table and got the default which is 36MHz instead of 16MHz.. So I have probably missed a divider in the data sheet, but still not close enough..

Last edited by Edstrom; 07/04/16 10:23 PM.
Because I can