Gah, I just started to look at the Force CPU-40 and it has the same FGA init but then the fun part starts with a table driven gibberish
setup of the DUSCC, dont't worry about the wrong baud rates, they make assumptions from CPU30 atm. There you go, a high level
language programmer has a table of constants and just changes the bits needed to get it to work. Compare that to the nice clean setup of the FGA in the beginning:

Code:
 * DUSCC #1 channel A setup 1 sequence FGA-002 firmware (polled i/o)
 *  A Reg 0f <- 00 - reset Tx Command
 *  A Reg 0f <- 40 - reset Rx Command
 *  A Reg 00 <- 07 - Async mode
 *  A Reg 01 <- 38 - Normal polled or interrupt mode, no DMA
 *  A Reg 04 <- 7f - Tx 8 bits, CTS and RTS, 1 STOP bit
 *  A Reg 06 <- 1b - Rx RTS, 8 bits, no DCD, no parity
 *  A Reg 05 <- 3d - Tx BRG 9600 (assuming a 14.7456 crystal)
 *  A Reg 07 <- 2d - Rx BRG 9600 (assuming a 14.7456 crystal)
 *  A Reg 0e <- 27 - TRxC = RxCLK 1x, RTxC is input, RTS, GPO2, crystal oscillator connected to X2
 *  A Reg 0b <- f1 - RTS low, OUT1 = OUT2 = high, RxRdy asserted on FIFO not empty
 *                   TxRdy asserted on FIFO not empty, Same Tx Residual Character Length as for REG_TPR
 *  A Reg 0f <- 00 - reset Tx Command
 *  A Reg 0f <- 40 - reset Rx Command
 *  A Reg 0f <- 02 - enable Tx Command
 *  A Reg 0f <- 42 - enable Rx Command
 *--- end of FGA setup sequence ---
 *  :dusccA Reg 00 <- ff CMR1 Async mode, no parity
 *  :dusccA Reg 01 <- 80 Local loopback mode
 *  :dusccA Reg 02 <- 20 Character Compare
 *  :dusccA Reg 03 <- 01 Not used in Async mode
 *  :dusccA Reg 08 <- 00 Counter/Timer Preset High 
 *  :dusccA Reg 09 <- 5f Counter/Timer Preset Low
 *  :dusccA Reg 0a <- 00 Counter Timer Control
 *  :dusccA Reg 0b <- 00 OMR 
Tx Residual Character Length is 1 bits
- TxRDY activated by FIFO not full
- RxRDY activated by FIFO not empty
- GP02, if configured as output, is: 1
- GP01, if configured as output, is: 1
- RTS, either pin if configured as output, is: 1
 *  :dusccA Reg 04 <- 00 TPR Transmit Parameter Register
- RTS 0
- CTS 0
- Stop Bits 1
- Data Tx bits 5
- RX:32x
- TX:32x
 *  :dusccA Reg 05 <- f0 
- External source: TRxC
- Transmit Clock: 32x own channel C/T - not implemented
- BRG Tx rate 50 assuming a 14.7456MHz CLK crystal
 *  :dusccA Reg 06 <- 00 
- RTS output 0      
- Strip Parity 0    
- DCD/SYNIN input 0 
- Data Rx bits 5    
- RX:32x  
- TX:1x   
 *  :dusccA Reg 07 <- 0a 
- External source: RTxC
- Receiver Clock: 1x External - not implemented
- BRG Rx rate 2000 assuming a 14.7456MHz CLK crystal
- RX:1x
- TX:1x
 *  :dusccA Reg 04 <- 00 
- RTS 0
- CTS 0
- Stop Bits 1
- Data Tx bits 5
- RX:32x
- TX:32x
 *  :dusccA Reg 05 <- f0 
- External source: TRxC
- Transmit Clock: 32x own channel C/T - not implemented
- BRG Tx rate 50 assuming a 14.7456MHz CLK crystal
 *  :dusccA Reg 06 <- 00 
- RTS output 0      
- Strip Parity 0    
- DCD/SYNIN input 0 
- Data Rx bits 5    
- RX:32x  
- TX:1x   
 *  :dusccA Reg 07 <- 8a 
- External source: TRxC
- Receiver Clock: 1x External - not implemented
- BRG Rx rate 2000 assuming a 14.7456MHz CLK crystal
- RX:1x
- TX:1x


Because I can