- CLOCK BIT: 00
* :upd7201:chaB 00 <- 18 Channel Reset command (011b)
* :upd7201:chbB 04 <- 4d Odd Parity enabled, Async mode 2 stop bits, 16x clock
* :upd7201:chbB 03 <- 41 Receiver enabled, 7 bit
* :upd7201:chbB 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
* :upd7201:chbB 01 <- 15 Interrupt on received character, Ext Status, status affect vector
* :upd7201:chbB 02 <- 00 No DMA, Non vectored interrupts D4 D3 D2, p10=RTSB
* :upd7201:chaA 00 <- 18 Channel Reset command (011b)
* :upd7201:chaA 02 <- 10 Interrupt vector
* :upd7201:chaA 04 <- 45 Odd Parity enabled, Async mode 1 stop bit, 16x clock rate
* :upd7201:chaA 03 <- 41 Receiver enabled, 7 bit
* :upd7201:chaA 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
* :upd7201:chaA 01 <- 10 Interrupt on received character
ff to COMM.CONTROL REGISTER
* :upd7201:chaA 00 <- 01