Sure, let me know if pin 34 is DATA OUT or COL25. Also, I'm assuming internal RAM(aka segments) are updated after each CLK. If it's different, eg. after CS goes high, or specifically after the last CLK, I'll have to change the emulation a bit. Also try overclocking(:D) to see if it's ignored, or segments are rewritten from the 1st bit.

elecdet: Back then, my verification routine wasn't as accurate so I'm not that surprised it had a bad bit. Tester report is here btw: