Here are my HLCD0569 experiment results:

Pin 21 is definitely column 12. I don't know why HRA doesn't use it.

Pin 34 is not data out. I'm not sure exactly what it is, but when /CS is high it outputs a signal at the same frequency as the row and column signals, but with double the duty cycle. When /CS is low it is low. Since there are no other unused pins, it doesn't appear that you can read the data out.

Segments are updated when /CS goes high for that row.

Init blank (mode 10) works the same as init visible (mode 11); the display is not blanked.

The last clock before /CS goes high is column 24, even if there are more or fewer than 24 clocks. First I "underclocked", and after sending the row and mode bits, sent six 0s followed by a 1, then raised /CS, repeated for each row. The segments for column 24 turned on. Then I sent a 1, five 0s and a 1, and segments 18 and 24 turned on.

Then I "overclocked" and sent 30 bits instead of 24. Again, the last clock was used for segment 24, and the previous 23 clocks were used for segments 23 to 1. The 6 clocks before those were discarded.