Thanks for the nudge in the right direction.
I now see a lot of lines with "Null command" and "CRC_RESET_NULL".
https://www.dropbox.com/s/6ss4f4g1d0mtlhe/Null_command.png?dl=0Stop bits, length (7), parity (none) seem to be correctly set.
What is totally absent -in the log- are RX and TX baud rates (at least values do not appear in 'update_serial').
Here the code section where i set an external baud rate generator from within Rainbow.cpp (2nd screenshot).
It uses the Com8116 baud rate generator Shattered recommended (#include "machine/com8116.h") -
// PORT 0x06 : Communication bit rates (see page 21 of PC 100 SPEC)
WRITE8_MEMBER(rainbow_state::comm_bitrate_w)
{
m_dbrg_A->str_w(data & 0x0f); // PDF is wrong, low nibble is RECEIVE clock (verified in SETUP).
printf("\n(COMM.) receive bitrate = %d ($%02x)\n", comm_rates[data & 0x0f] , data & 0x0f);
m_dbrg_A->stt_w( ((data & 0xf0) >> 4) );
printf("(COMM.) transmit bitrate = %d ($%02x)\n", comm_rates[((data & 0xf0) >> 4)] ,(data & 0xf0) >> 4);
}
// PORT 0x0e : Printer bit rates
WRITE8_MEMBER(rainbow_state::printer_bitrate_w)
{
m_dbrg_B->str_w(data & 7); // bits 0 - 2
m_dbrg_B->stt_w(data & 7); // TX and RX rate cannot be programmed independently.
printf("\n(PRINTER) receive = transmit bitrate: %d ($%02x)", 9600 / ( 1 << (7 - (data & 7))) , data & 7);
// "bit 3 controls the communications port clock (RxC,TxC). External clock when 1, internal when 0"
printf(" - CLOCK (0 = internal): %02x", data & 8);
}
Maybe something is missing?
There is also an odd clock bit (not part of the Z80SIO, must be external circuitry) not handled yet (normally zero).
See printer_bitrate_w above.
Log from screenshot (as text):
Z80SIO ":upd7201_new" Channel B : CRC_RESET_NULL
* :upd7201_new:chb B Reg 02 <- 00 - WR2
void z80sio_channel::control_write(uint8_t)(00) reg 02
Z80SIO ":upd7201_new" Channel B : Interrupt Vector 00
(COMM.) receive bitrate = 1200 ($08)
(COMM.) transmit bitrate = 1800 ($09)
void z80sio_channel::control_write(uint8_t)(02) reg 00
void z80sio_channel::do_sioreg_wr0(uint8_t) :upd7201_new:cha Ch:A : Null command
void z80sio_channel::do_sioreg_wr0_resets(uint8_t) :upd7201_new:cha
Z80SIO ":upd7201_new" Channel A : CRC_RESET_NULL
* :upd7201_new:cha A Reg 02 <- 10 - WR2
void z80sio_channel::control_write(uint8_t)(10) reg 02
Z80SIO ":upd7201_new" Channel A : Interrupt Vector 10
void z80sio_channel::control_write(uint8_t)(04) reg 00
void z80sio_channel::do_sioreg_wr0(uint8_t) :upd7201_new:cha Ch:A : Null command
void z80sio_channel::do_sioreg_wr0_resets(uint8_t) :upd7201_new:cha
Z80SIO ":upd7201_new" Channel A : CRC_RESET_NULL
* :upd7201_new:cha A Reg 04 <- 44 - WR4 - Async Clock, Parity and stop bits
void z80sio_channel::control_write(uint8_t)(44) reg 04
Z80SIO ":upd7201_new" Channel A : Parity Enable 0
Z80SIO ":upd7201_new" Channel A : Parity Odd
device_serial_interface::stop_bits_t z80sio_channel::get_stop_bits() :upd7201_ne
w:cha
1 STOP BIT.Z80SIO ":upd7201_new" Channel A : Stop Bits 1
Z80SIO ":upd7201_new" Channel A : Clock Mode 16X
int z80sio_channel::get_rx_word_length() :upd7201_new:cha
Z80 SIO) receive word length: 07device_serial_interface::stop_bits_t z80sio_chan
nel::get_stop_bits() :upd7201_new:cha
1 STOP BIT.void z80sio_channel::update_serial()
(Z80SIO) : data_frame (data_bit_count = 07), parity = 00, stop_bits = 01
void z80sio_channel::control_write(uint8_t)(03) reg 00
void z80sio_channel::do_sioreg_wr0(uint8_t) :upd7201_new:cha Ch:A : Null command
void z80sio_channel::do_sioreg_wr0_resets(uint8_t) :upd7201_new:cha
Z80SIO ":upd7201_new" Channel A : CRC_RESET_NULL
* :upd7201_new:cha A Reg 03 <- 41 - WR3 - Async Rx setup
void z80sio_channel::control_write(uint8_t)(41) reg 03
Z80SIO ":upd7201_new" Channel A : Receiver Enable 1
Z80SIO ":upd7201_new" Channel A : Auto Enables 0
int z80sio_channel::get_rx_word_length() :upd7201_new:cha
Z80 SIO) receive word length: 07Z80SIO ":upd7201_new" Channel A : Receiver Bits/
Character 7
int z80sio_channel::get_rx_word_length() :upd7201_new:cha
Z80 SIO) receive word length: 07device_serial_interface::stop_bits_t z80sio_chan
nel::get_stop_bits() :upd7201_new:cha
1 STOP BIT.void z80sio_channel::update_serial()
(Z80SIO) : data_frame (data_bit_count = 07), parity = 00, stop_bits = 01
void z80sio_channel::control_write(uint8_t)(05) reg 00
void z80sio_channel::do_sioreg_wr0(uint8_t) :upd7201_new:cha Ch:A : Null command
void z80sio_channel::do_sioreg_wr0_resets(uint8_t) :upd7201_new:cha
Z80SIO ":upd7201_new" Channel A : CRC_RESET_NULL
* :upd7201_new:cha A Reg 05 <- 28 - WR5 - Async Tx setup
void z80sio_channel::control_write(uint8_t)(28) reg 05
Z80SIO ":upd7201_new" Channel A : Transmitter Enable 1
int z80sio_channel::get_tx_word_length() :upd7201_new:cha
Z80 SIO) transmit word length: 07Z80SIO ":upd7201_new" Channel A : Transmitter B
its/Character 7
Z80SIO ":upd7201_new" Channel A : Send Break 0
Z80SIO ":upd7201_new" Channel A : Request to Send 0
Z80SIO ":upd7201_new" Channel A : Data Terminal Ready 0
int z80sio_channel::get_rx_word_length() :upd7201_new:cha
Z80 SIO) receive word length: 07device_serial_interface::stop_bits_t z80sio_chan
nel::get_stop_bits() :upd7201_new:cha
1 STOP BIT.void z80sio_channel::update_serial()
(Z80SIO) : data_frame (data_bit_count = 07), parity = 00, stop_bits = 01void z80
sio_channel::update_rts()() ":upd7201_new" Channel A
void z80sio_channel::set_dtr(int)(1)
