That SMC1112 is interesting =) I hope that the LCD opcodes are same as in TI's chips(of which no documentation is available). Looks like TDO is changed to TASR(ACC to LCD-shiftreg), and 4 opcodes(TSG1-4) to transfer shiftreg to 4 commons.
The array is 64 rows tall by 256 columns wide. It looks like the 64 rows are the 6 bits of the PC, and the 256 columns are 32 banks (1 chapter bit and 4 page bits) of each of the 8 data bits. Five bits of the ROM word decoder to the left of the array looks like they are in sequence 00000-11111, but I'm not sure how the 6th bit is used. I also don't understand the bank decoder circuit that's repeated 8 times across the top of the array. I see a 1, 2, 4, 8 pattern, but don't see how it selects one of the 32 columns.
It looks like the leftmost group of 32 columns is the high bit, since it has the lowest bit density, like most TMS1100 ROMs. Of course the groups might not be in bit order, but I rearranged the raw bits that way, and by assuming the rows are in order and the banks are in order. That could be correct for the rows, but I'm pretty sure that's incorrect for the columns. I'm just not sure how the column selector works; it looks like 1/2 the contacts in the circuits are missing. If I put those in where it looks like they are missing, then I get the column order 5, 4, 7, 6, 1, 0, 3, 2, D, C, F, E, 9, 8, B, A, 15, 14, 17, 16, 11, 10, 13, 12, 1D, 1C, 1F, 1E, 19, 18, 1B, 1A.
