I'm trying to emulate the HH Tiger, the ROMs were dumped from http://www.computinghistory.org.uk/det/52264/HH-Tiger/ at the weekend. There's not much out there about this rare machine (I hear only 12 made) so all I have are the ROMs and a few photos I took of the internals to identify the components and crystals.

See advert on page 150-151 at https://ia600801.us.archive.org/34/...tical%20Computing%201983%20July%2007.pdf

Here's what I now know and have running so far:
Z80A-CPU @ 16MHz / 4
Z80A-DMA
Z80A-PIO - interface with 6809
64K RAM
4K ROM
The Z80 boots from a 4K ROM which is mirrored throughout the address space at startup. A read from IO port $1E replaces the address space with 64K RAM and the ROM is still mapped at $F000-$FFFF.

MC68B09 @ 16MHz / 8
SY6522A VIA x 2 - 1 for printer (centronics) port, other for Z80 interface
NEC uPD7220 graphics processor - 96K video RAM, 512x512 = 32K/bitplane
MC68B54 - Network ports
SY6551A - RS232 @ 1.8432MHz
TMS9914 - GPIB (IEEE-488)
The 6809 boots from 2x8K ROM at $C000-$FFFF, it also has 2K RAM ($0000-$07FF maybe) and $200 bytes CMOS battery backed RAM.

I didn't identify any sound hardware, but I've seen photos of other examples with an internal speaker. There are also connectors for 3 floppy drives but didn't see any FDC in there, but have seen photos where the floppy drives are housed with the monitor (which the museum doesn't have) so maybe the FDC is external too.

I believe I have all devices memory mapped correctly, the 6809 definitely configures the uPD7220 sensibly.
Code
//-------------------------------------------------
//  ADDRESS_MAP( z80_mem )
//-------------------------------------------------

void hhtiger_state::z80_mem(address_map &map)
{
	map(0x0000, 0xffff).rw(FUNC(hhtiger_state::read), FUNC(hhtiger_state::write));
}

void hhtiger_state::z80_io(address_map &map)
{
	map.global_mask(0xff);
	map(0x00, 0x03).rw(m_dma, FUNC(z80dma_device::bus_r), FUNC(z80dma_device::bus_w));
	map(0x04, 0x07).rw(m_pio, FUNC(z80pio_device::read), FUNC(z80pio_device::write));
	map(0x10, 0x17).rw(m_tms9914, FUNC(tms9914_device::read), FUNC(tms9914_device::write)); // ??
	map(0x1e, 0x1e).r(FUNC(hhtiger_state::disable_rom_r));
}


//-------------------------------------------------
//  ADDRESS_MAP( m6809_mem )
//-------------------------------------------------

void hhtiger_state::m6809_mem(address_map &map)
{
	map(0x0000, 0x07ff).ram();
	map(0xb800, 0xb9ff).ram().share("nvram");
	map(0xbfa0, 0xbfa1).rw(m_gdc, FUNC(upd7220_device::read), FUNC(upd7220_device::write));
	map(0xbfb0, 0xbfb3).rw(m_adlc, FUNC(mc6854_device::read), FUNC(mc6854_device::write)); // ??
	map(0xbfc0, 0xbfcf).m(m_via[1], FUNC(via6522_device::map));
	map(0xbfd0, 0xbfd3).rw(m_acia, FUNC(mos6551_device::read), FUNC(mos6551_device::write)); // ??
	map(0xbfe0, 0xbfef).m(m_via[0], FUNC(via6522_device::map));
	map(0xc000, 0xffff).rom().region("rom_m6809", 0);
}


What I'm struggling with is the communication between the two CPU's with the Z80 PIO and a 6522 VIA. Anyone have any experience with setting up communication with these devices, or any suggestion as to how it may be implemented? The PIO seems to be setup with port A being bi-directional with port A on one of the 6522's, and PIO port B (bit3) seems to be writing to 6522 CA1. I don't yet have any clues on how the 6522 tells the PIO it has data ready.

If I don't make any further progress soon then I'll submit what I have for anyone else to take a look.

I don't expect the machine to do much apart from prompting to insert a CP/M system disk, which I don't have.

Last edited by Pernod; 07/09/19 08:59 PM.

BBC Model B, ATPL Sidewise, Acorn Speech, 2xWatford Floppy Drives, AMX Mouse, Viglen case, etc.