Originally Posted by Edstrom
Originally Posted by Luigi30
Yeah, I don’t have bus arbitration yet but I have /DTACK and a couple other signals. The ‘320 and ‘120 are both capable of bus mastering under my vme.cpp. A card can assert a signal line which gets distributed to all attached cards on the backplane as a callback for them to override (or ignore if they don’t care).

Cool, I think the challenge with DTACK is how to suspend the CPU board until you'll get the DTACK in a good way, especially as the M68000 core didn't have DTACK support last time I checked at least, so emulate that by eating cycles. Also it is a good thing to put common stuff in the VME device and just parameterize it. Often DTACK has different timing for each device on a board so the DTACK value should really be property on the memory map but I am unsure if any VME boards had split DTACK values or just had one for its entire VME window.

Right, the way I have it set up is that the 120 will halt waiting for DTACK until it either times out (the board will pulse BERR if the bus cycle isn't complete after 220ns) or it's asserted on the bus. There's a bunch of logic on the 120 to figure out which DTACK we're waiting for but at the moment it only cares about the one from the bus. I have the halt set up using a timer/spin_until_trigger combo.

Originally Posted by Edstrom
Many MAME systems do have problems with self tests and it can be for various reasons but timing is a difficult one when not having proper DTACK support in the CPU core. ROM hacks are not ok to submit I believe unless you do it live, that is having a proper ROM and patch it during startup, many systems seems to do that.

Right, it patches live during startup to bypass one specific test (replacing a branch with a NOP like all good hacks).

Last edited by Luigi30; 12/25/21 09:02 PM.