I'll need to know how to sync the PLL either way!
When I started, I didn't realize the board did things like stretch the clock phases to match the processor speed with the floppy data rate. I reverse-engineered parts of the firmware and made the 8X305 core subcycle-accurate to get it this far, but this is far, far
above my experience level. I'm a programmer, not an analog hardware guru.
I don't want to leave it as-is but I haven't been able to make substantial progress on emulating the PLL and the other microcoded subsystem clocked by it
that actually interact with the floppy drive.