AICA has several clock inputs. The primary one is 33.8688MHz coming from GD-ROM. It gets multiplied by *2 PLL for SPU SDRAM (connected trough 16-bit wide bus).
There's another PLL loop doing 2/3 on that clock so it ends up as 22579200Hz. This is AICA CORE clock and is not to be confused with 25MHz that AICA receives as the G2 bus clock (which BTW is 16-bit wide and that sums up to 50MB/s, however due to FIFO restrictions it can do 40 at most on real hardware). There is yet another clock from GD, about 2MHz, it carries CD-DA data. Not really important. And lets not forget the 32768Hz crystal being reference for RTC - and well, nothing else.
I guess I should also mention one more PLL doing 22579200/2 = 11289600 clock that goes to DAC. And that's exactly 256 * 44100, should anyone care.
AICA ARM7 speed is limited by it's ability to access memory. It can do so only once per 8 cycles of AICA CORE clock, as DAC and DSP take the rest. Guess it saves a bunch of transistors on the memory controller. ARM has no cache and must fetch opcode for every instruction as it goes, so it limits at 2822400 IPS. Now, every LDR/STR instruction does another read/write, and that slows it down even more. Same goes for block register reads/stores.
You could either go for cycle-exact (defining cycle as memory access) as Makaron does now, or try a mean of 1.4-1.6 MIPS because that's approximately how fast a typical code would run.
I suppose some of us "cookbook chefs" actually do come up with recipes of our own... Luckily this isn't in MAME yet so I don't have to prove I've ripped someone else's preciuos code.
