Say, you wouldn't happen to know why is INPUTS being overwritten when IRA == IWA on IWT? Does it mean MEMS write happens first? Could be, but there's nothing on it in AICA docs (or Neill's). Something found in Saturn specs?
I'm not sure what is the correct way to handle this nor am I aware of any documentation that addresses this issue. I did look through a quick sampling of various ssfs and didn't see any meaningful DSP instructions where IWT==IRA.
Originally Posted By Deunan Knute
kingshriek, as I understand AO uses parts of MANATEE to play DSFs? Would it be possible to create some sort of patcher that would go over dumped RAM image and hack ARM program to mask DISDL writes to zero?
Try replacing the following two consecutive instructions: