Well, you guys are kicking butt here, so I had to mention it. I don't expect it to be a valid bug for long, with the way you and etabeta78 are ripping through some of the fundamentals of rendering and register accesses.

I'm having no luck on my NES projects, so I'll see if I can't find any obvious ways to help out here smile

Edit 1: Probably the single biggest "quick fix" for timing being very off is that DMA takes 0 cycles. while the proper figure is (length+1) for the transfer itself, there is some overhead (I can't find byuu's *DMA data any better than I can keep up with his IRQ timing data to give exact figures)

Last edited by Heretical_One; 08/10/09 12:26 AM.